Patents by Inventor Shigeo Oomae

Shigeo Oomae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7911769
    Abstract: This invention prevents a deterioration of efficiency of a power supply apparatus due to a semiconductor power supply voltage drop, prevents an increase in wasted power, and prevents erroneous operations due to feeder wire voltage drop. In the mounting structure of electronic circuits having a plurality of busbars as current paths on a printed circuit board, the plurality of busbars have almost parallel portions spaced a predetermined distance apart; a span of the parallel portions of the plurality of busbars is greater than the predetermined distance; and in the parallel portions of the plurality of busbars, the plurality of busbars are connected by a wiring pattern. In the switching power supply apparatus built on a printed circuit board, with its output voltage of less than 2 V and its output current of more than 100 A, a means is provided for making the power efficiency higher than 70%.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: March 22, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Hideho Yamamura, Naoki Maru, Kazunori Nakajima, Koji Nisisu, Shigeo Oomae
  • Publication number: 20090257210
    Abstract: This invention prevents a deterioration of efficiency of a power supply apparatus due to a semiconductor power supply voltage drop, prevents an increase in wasted power, and prevents erroneous operations due to feeder wire voltage drop. In the mounting structure of electronic circuits having a plurality of busbars as current paths on a printed circuit board, the plurality of busbars have almost parallel portions spaced a predetermined distance apart; a span of the parallel portions of the plurality of busbars is greater than the predetermined distance; and in the parallel portions of the plurality of busbars, the plurality of busbars are connected by a wiring pattern. In the switching power supply apparatus built on a printed circuit board, with its output voltage of less than 2 V and its output current of more than 100 A, a means is provided for making the power efficiency higher than 70%.
    Type: Application
    Filed: June 18, 2009
    Publication date: October 15, 2009
    Inventors: Hideho Yamamura, Naoki Maru, Kazunori Nakajima, Koji Nisisu, Shigeo Oomae
  • Patent number: 7548411
    Abstract: This invention prevents a deterioration of efficiency of a power supply apparatus due to a semiconductor power supply voltage drop, prevents an increase in wasted power, and prevents erroneous operations due to feeder wire voltage drop. In the mounting structure of electronic circuits having a plurality of busbars as current paths on a printed circuit board, the plurality of busbars have almost parallel portions spaced a predetermined distance apart; a span of the parallel portions of the plurality of busbars is greater than the predetermined distance; and in the parallel portions of the plurality of busbars, the plurality of busbars are connected by a wiring pattern. In the switching power supply apparatus built on a printed circuit board, with its output voltage of less than 2 V and its output current of more than 100 A, a means is provided for making the power efficiency higher than 70%.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: June 16, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Hideho Yamamura, Naoki Maru, Kazunori Nakajima, Koji Nisisu, Shigeo Oomae
  • Patent number: 7277643
    Abstract: A signal communication apparatus of a clock reproduction system in which clock signals are extracted from each of parallel data signals for redigitizing each of the data signals. The apparatus includes a reference clock signal generating circuit which is comprised of a clock extraction circuit for extracting a clock signal from each of a plurality of bits of received data signals, and a clock signal selection circuit for selecting one of the extracted clock signals. Alternatively, the reference clock signal generating circuit may be comprised of a data signal selection circuit for selecting one of a plurality of received data signals, and a clock extraction circuit for extracting a clock signal from the selected bit. Based on the resultant reference clock signal, clock signals are obtained that are phase-adjusted for redigitizing each bit of the received data signals.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: October 2, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Takashige Baba, Tatsuya Saito, Masayoshi Yagyu, Shigeo Oomae
  • Patent number: 7208883
    Abstract: In the current detection circuit that detects the output currents of a switching power supply circuit, an improved current detection circuit makes it possible to detect the output current directions of power supplies solves the malfunction of the power supplies vibrating or diverging during changes in load state and during parallel operation, and thus implements stable operation. The direction of an output current I2 can be detected by using the current detection circuit 8 that has multiple switching elements S1 to S4 each operating synchronously with an inverter circuit.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: April 24, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Maru, Hideho Yamamura, Koji Nisisu, Shigeo Oomae
  • Publication number: 20060132062
    Abstract: In the current detection circuit that detects the output currents of a switching power supply circuit, an improved current detection circuit makes it possible to detect the output current directions of power supplies solves the malfunction of the power supplies vibrating or diverging during changes in load state and during parallel operation, and thus implements stable operation. The direction of an output current I2 can be detected by using the current detection circuit 8 that has multiple switching elements S1 to S4 each operating synchronously with an inverter circuit.
    Type: Application
    Filed: December 5, 2005
    Publication date: June 22, 2006
    Inventors: Naoki Maru, Hideho Yamamura, Koji Nisisu, Shigeo Oomae
  • Publication number: 20060092599
    Abstract: This invention prevents a deterioration of efficiency of a power supply apparatus due to a semiconductor power supply voltage drop, prevents an increase in wasted power, and prevents erroneous operations due to feeder wire voltage drop. In the mounting structure of electronic circuits having a plurality of busbars as current paths on a printed circuit board, the plurality of busbars have almost parallel portions spaced a predetermined distance apart; a span of the parallel portions of the plurality of busbars is greater than the predetermined distance; and in the parallel portions of the plurality of busbars, the plurality of busbars are connected by a wiring pattern. In the switching power supply apparatus built on a printed circuit board, with its output voltage of less than 2 V and its output current of more than 100 A, a means is provided for making the power efficiency higher than 70%.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 4, 2006
    Inventors: Hideho Yamamura, Naoki Maru, Kazunori Nakajima, Koji Nisisu, Shigeo Oomae
  • Publication number: 20060082422
    Abstract: A connection structure is applied to mutually connect a first and a second transmission line that is planar in shape and that has a ground conductor on a second main surface, such as a microstrip line or a coplanar line with a ground. The first and the second transmission lines are superposed one upon the other, and their signal wiring patterns are electrically connected, as are their ground conductors. An end surface of the first transmission line is substantially covered by a conductor layer connected to the ground conductor. The connection structure can achieve good signal transmission characteristics up to high-frequency bands on the order of several tens of gigahertz.
    Type: Application
    Filed: October 3, 2005
    Publication date: April 20, 2006
    Inventors: Masayoshi Yagyu, Tatsuya Saito, Shigeo Oomae, Mitsuo Akashi
  • Publication number: 20050174190
    Abstract: A connection structure is applied to mutually connect a first and a second transmission line that is planar in shape and that has a ground conductor on a second main surface, such as a microstrip line or a coplanar line with a ground. The first and the second transmission lines are superposed one upon the other, and their signal wiring patterns are electrically connected, as are their ground conductors. An end surface of the first transmission line is substantially covered by a conductor layer connected to the ground conductor. The connection structure can achieve good signal transmission characteristics up to high-frequency bands on the order of several tens of gigahertz.
    Type: Application
    Filed: July 29, 2003
    Publication date: August 11, 2005
    Inventors: Masayoshi Yagyu, Tatsuya Saito, Shigeo Oomae, Mitsuo Akashi
  • Publication number: 20040109476
    Abstract: A signal communication apparatus of a clock reproduction system in which clock signals are extracted from each of parallel data signals for redigitizing each of the data signals. The apparatus includes a reference clock signal generating circuit which is comprised of a clock extraction circuit for extracting a clock signal from each of a plurality of bits of received data signals, and a clock signal selection circuit for selecting one of the extracted clock signals. Alternatively, the reference clock signal generating circuit may be comprised of a data signal selection circuit for selecting one of a plurality of received data signals, and a clock extraction circuit for extracting a clock signal from the selected bit. Based on the resultant reference clock signal, clock signals are obtained that are phase-adjusted for redigitizing each bit of the received data signals.
    Type: Application
    Filed: July 30, 2003
    Publication date: June 10, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Takashige Baba, Tatsuya Saito, Masayoshi Yagyu, Shigeo Oomae