Abstract: A semiconductor memory device is provided in which an electrode applied with the power supply voltage or the ground voltage is provided on an insulating layer over the drain and/or the gate of the MOS transistors constituting the memory cell of a static memory device, thereby to increasing the capacitance of the storing node of the memory cell. This semiconductor memory device significantly reduces the occurrence of soft errors.

Abstract: A semiconductor memory device having a memory plane defined by a plurality of memory cells, a decoder line for accessing the memory cells, a common data line on which a signal output from an accessed memory cell is collected, and a sense amplifier for amplifying the signal collected on the common data line. The sense amplifier has an amplifying circuit portion which is composed of a pair of common-collector type bipolar transistors supplied with the signal collected on the common data line as a differential input, and a plurality of MOS transistors for converting a change in current into a change in voltage. Each of the MOS transistors has a lightly-doped drain structure.

Abstract: Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions of the two driver MOS transistors in each memory cell are connected in common and further connected to a ground potential point through a second-level conductive layer. The two load resistances in each memory cell are formed from a third-level high-resistance material layer. The second-level conductive layer is formed from a low-resistance material layer. Thus the resistance of the sources of the two driver MOS transistors is lowered.

Abstract: A resistance element having a reduced occupied area and a high resistance which may be employed as a load resistor used in, for example, a static memory device. A high-resistance area is formed using a relatively thin film, while an interconnection area is formed using a relatively thick film, and these films are provided in such a manner that the thin film is in contact with the upper side of the thick film (the relatively thick film is a first-level film, and the relatively thin film is a second-level film).

Abstract: A semiconductor memory is provided with automatic refresh means including a timer, a refresh counter and a refresh buffer each formed on a semiconductor chip mounted with an asynchronous memory, for automatically performing a periodic refresh operation on the basis of a basic clock signal which is generated in response to the detection of a logical change in the output of the refresh counter. The automatic refresh counter includes means for performing one of a read operation and a write operation which are based upon a regular address signal asynchronous with the periodic refresh operation, in preference to the periodic refresh operation.