Patents by Inventor Shigeru Kambayashi

Shigeru Kambayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7239278
    Abstract: A detection system includes a sensitiveness level setup control section and a receiver control section. The sensitiveness level setup control section looks into a sensitiveness level setup file and finds the sequence of levels of sensitiveness to the received signals corresponding to the setup ID. The receiver control section converts, for each component, a sequence of levels of sensitiveness to received signals received from the sensitiveness level switching section into signals for designating levels of sensitiveness to received signals corresponding to the respective receivers, and transmits the signals for designating levels of sensitiveness to received signals through the communication network.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: July 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Koiso, Kanako Hattori, Naoki Imasaki, Shigeru Kambayashi
  • Publication number: 20050046577
    Abstract: A detection system includes a sensitiveness level setup control section and a receiver control section. The sensitiveness level setup control section looks into a sensitiveness level setup file and finds the sequence of levels of sensitiveness to the received signals corresponding to the setup ID. The receiver control section converts, for each component, a sequence of levels of sensitiveness to received signals received from the sensitiveness level switching section into signals for designating levels of sensitiveness to received signals corresponding to the respective receivers, and transmits the signals for designating levels of sensitiveness to received signals through the communication network.
    Type: Application
    Filed: July 7, 2004
    Publication date: March 3, 2005
    Inventors: Takashi Koiso, Kanako Hattori, Naoki Imasaki, Shigeru Kambayashi
  • Patent number: 6395621
    Abstract: A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate a exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: May 28, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Yuichiro Mitani, Shigeru Kambayashi, Kiyotaka Miyano
  • Publication number: 20020034864
    Abstract: A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth.
    Type: Application
    Filed: December 3, 2001
    Publication date: March 21, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Yuichiro Mitani, Shigeru Kambayashi, Kiyotaka Miyano
  • Patent number: 6346732
    Abstract: A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: February 12, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Yuichiro Mitani, Shigeru Kambayashi, Kiyotaka Miyano
  • Patent number: 6342421
    Abstract: A method of manufacturing a semiconductor device including the steps of forming an insulating film on a silicon region of a substrate having the silicon region on a surface the insulating film having an opening for forming an exposed region of the silicon region, supplying a gas containing a halogen onto the silicon region, and supplying a source gas of silicon onto the silicon region, thereby selectively depositing the silicon on the exposed region of the silicon region.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: January 29, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Ichiro Mizushima, Shigeru Kambayashi, Hirotaka Nishino, Masahiro Kashiwagi
  • Patent number: 6093243
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: July 25, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 6066872
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: May 23, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 6018185
    Abstract: The semiconductor device comprises a semiconductor substrate having an element region, an element isolation film formed on the semiconductor substrate so as to surround the element region, a gate portion crossing the element region and extending over the semiconductor substrate, the gate portion comprising at least a gate insulation film formed on the semiconcuctor substrate and a gate electrode formed on the gate insulation film, and source/drain regions formed on the surface of the element regions on both sides of the gate portion, wherein an upper surface of the element isolation film is formed in substantially the same plane as an upper surface of the gate portion.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: January 25, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Ichiro Mizushima, Shigeru Kambayashi, Iwao Kunishima, Masahiro Kashiwagi
  • Patent number: 5981150
    Abstract: The present invention provides a method for forming a resist pattern which allows a closest pattern to be formed thus solving a problem of misalignment. A substrate has, on the surface thereof, first and second domains having different reflectivity to first light. A resist covers the first and second domains. The first light illuminates the resist and reflects from the surfaces of the first and second domains. A resist pattern forms in the fashion of self-alignment based on the illuminated and reflected light. The sum of the exposure of the illuminated and reflected light is set above a threshold of exposure by which the resist is sensitized in the first domain and set below the threshold of exposure in the second domain.
    Type: Grant
    Filed: July 3, 1997
    Date of Patent: November 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masami Aoki, Shigeru Kambayashi, Junichi Wada, Yasuhiko Sato
  • Patent number: 5879447
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 5864161
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming an insulating film on a silicon region of a substrate having the silicon region on a surface the insulating film having an opening for forming an exposed region of the silicon region, supplying a gas containing a halogen onto the silicon region, and supplying a source gas of silicon onto the silicon region, thereby selectively depositing the silicon on the exposed region of the silicon region.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: January 26, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Ichiro Mizushima, Shigeru Kambayashi, Hirotaka Nishino, Masahiro Kashiwagi
  • Patent number: 5582640
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: December 10, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano