Abstract: A display system uses a dual-port memory having a random access memory part and a serial access memory part as a frame buffer. Display data is transferred from the random access memory part to the serial access memory part in response to a timing signal of the data transfer. Just prior to the timing signal, an access start disable signal is generated, which has an active period being equal to or longer than an access cycle time of drawing data. When the access start disable signal is active, a draw access from a central processing unit, etc. to the dual port memory becomes disable. Further, address bits for a column of the memory are detected to become all zero and a predetermined value, so that the timing of a real time data transfer and the access start disable signal for the real time data transfer can be generated.

Abstract: An inverter for converting DC power to AC power, an oscillation control circuit for stepwise generating a command value concerning the conversion condition of the inverter, and an operation controller which, when the command value from the oscillation control circuit changes, controls the oscillation control circuit to repetitively generate alternate new and old or present command values before and after change of the command value. Particularly, this invention provides an inverter capable of continuing smooth operation even when the control system has a limited resolution.