Abstract: A semiconductor device including an input terminal to which a power source, for which the time until a voltage equal or greater than a predetermined voltage value is output fluctuates according to an external environment, is connected, a power source section to which the input terminal supplies power from the power source, a power source supply terminal that supplies power to a driven semiconductor device, a switch that controls a connection between the power source section and the power source supply terminal, and a voltage regulator to which the input terminal supplies power from the power source, and that supplies a voltage to the power source supply terminal is provided.

Abstract: A semiconductor device includes a setting circuit and a reset circuit. The setting circuit includes a latch circuit having first and second inverters driven by a first power voltage whose level is fixed and a first transistor which is switched between an ON state and an OFF state on the basis of a level of a second power voltage whose level varies depending on a surrounding environment, and sets data corresponding to a reference voltage to the latch circuit in response to the first transistor being switched to the ON state. The reset circuit includes an N-type second transistor connected to an output of the first inverter and an input of the second inverter. The second transistor sets data corresponding to the reference voltage to the latch circuit in response to the second voltage being equal to or lower than a predetermined voltage value.

Abstract: A semiconductor device including an input terminal to which a power source, for which the time until a voltage equal or greater than a predetermined voltage value is output fluctuates according to an external environment, is connected, a power source section to which the input terminal supplies power from the power source, a power source supply terminal that supplies power to a driven semiconductor device, a switch that controls a connection between the power source section and the power source supply terminal, and a voltage regulator to which the input terminal supplies power from the power source, and that supplies a voltage to the power source supply terminal is provided.

Abstract: A semiconductor device including an input terminal to which a power source, for which the time until a voltage equal or greater than a predetermined voltage value is output fluctuates according to an external environment, is connected, a power source section to which the input terminal supplies power from the power source, a power source supply terminal that supplies power to a driven semiconductor device, a switch that controls a connection between the power source section and the power source supply terminal, and a voltage regulator to which the input terminal supplies power from the power source, and that supplies a voltage to the power source supply terminal is provided.

Abstract: A semiconductor device includes a setting circuit and a reset circuit. The setting circuit includes a latch circuit having first and second inverters driven by a first power voltage whose level is fixed and a first transistor which is switched between an ON state and an OFF state on the basis of a level of a second power voltage whose level varies depending on a surrounding environment, and sets data corresponding to a reference voltage to the latch circuit in response to the first transistor being switched to the ON state. The reset circuit includes an N-type second transistor connected to an output of the first inverter and an input of the second inverter. The second transistor sets data corresponding to the reference voltage to the latch circuit in response to the second voltage being equal to or lower than a predetermined voltage value.

Abstract: A semiconductor device including an input terminal to which a power source, for which the time until a voltage equal or greater than a predetermined voltage value is output fluctuates according to an external environment, is connected, a power source section to which the input terminal supplies power from the power source, a power source supply terminal that supplies power to a driven semiconductor device, a switch that controls a connection between the power source section and the power source supply terminal, and a voltage regulator to which the input terminal supplies power from the power source, and that supplies a voltage to the power source supply terminal is provided.

Abstract: A semiconductor integrated circuit includes constant current circuit, starter circuit and power supply start-up circuit. In the constant current circuit, first current mirror circuit includes first and second transistors, and second current mirror circuit includes third and fourth transistors that are connected to first and second nodes. In the starter circuit, a potential of first node controls sixth transistor, seventh transistor is connected to third node, gate electrode of the seventh transistor is at ground potential, a capacitance element is connected to fourth node, and a potential of fourth node controls fifth transistor, which supplies start-up current to the constant current circuit via second node. In the power supply start-up circuit, source electrode of eighth transistor is fixed at power supply voltage, gate electrode is at ground potential, and drain electrode supplies power to the other circuits.

Abstract: A semiconductor integrated circuit includes constant current circuit, starter circuit and power supply start-up circuit. In the constant current circuit, first current mirror circuit includes first and second transistors, and second current mirror circuit includes third and fourth transistors that are connected to first and second nodes. In the starter circuit, a potential of first node controls sixth transistor, seventh transistor is connected to third node, gate electrode of the seventh transistor is at ground potential, a capacitance element is connected to fourth node, and a potential of fourth node controls fifth transistor, which supplies start-up current to the constant current circuit via second node. In the power supply start-up circuit, source electrode of eighth transistor is fixed at power supply voltage, gate electrode is at ground potential, and drain electrode supplies power to the other circuits.

Abstract: A semiconductor integrated circuit includes a constant current circuit and a start-up circuit. The constant current circuit includes a first current mirror circuit including a first and second transistors; and a second current mirror circuit including a third transistor connected to a first node and a fourth transistor connected to a second node. The start-up circuit includes a fifth transistor that supplies start-up current to the constant current circuit via the second node; a sixth transistor that uses a potential of the first node as a control voltage; a seventh transistor that is connected to a third node into which current from the sixth transistor flows and that has a diode-connected configuration; a capacitor connected to a fourth node into which current from the seventh transistor flows; and a latch circuit that controls the fifth based on a potential of the fourth node.

Abstract: A driving circuit of a display device is provided. In a first time period of a data writing period, a control section of the driving circuit effects control so as to short-circuit a first node which is set to a target gradation potential and a node (second node) adjacent to the first node, and such that a line (second line) between the second node and a hold capacitor of a pixel is connected in parallel to a line (first line) between the first node and the hold capacitor of the pixel. Further, in a second time period following the first time period, the control section controls switching element groups so as to cancel short-circuiting between the first node and the second node, and such that the second line is not connected in parallel to the first line.

Abstract: A first output section of a reference voltage output circuit outputs a negative gradient voltage of a first magnitude. An amplifier includes a non-inverting input terminal connected to the first output section, an inverting input terminal, and an output terminal. One end of a first resistor connected to the output terminal and the other end connected to the inverting input terminal. One end of a second resistor is connected to the other end of the first resistor. A second output section connected to the other end of the second resistor outputs a negative gradient voltage of a second magnitude having an absolute value greater than the first magnitude. A resistance value ratio of the first and second resistors is set such that a temperature gradient of the voltage applied to the first resistor is a positive gradient having an absolute value of the same magnitude as the first magnitude.

Abstract: The present invention provides a charge-pump boosting circuit. In a charging period of a capacitor C1, a PMOS transistor Q1 and an NMOS transistor Q2 turn on, and the capacitor C1 is charged by voltage between a potential VCC and a potential VSS. On the other hand, in a discharging period of a boosting capacitor, a PMOS transistor Q3 and a PMOS transistor Q4 turn on, and charges accumulated in the boosting capacitor are discharged. In a discharging period of the capacitor C1, a selector SEL1 selects a terminal T1, and a feedback system, in which operation voltage applied to a gate of the PMOS transistor Q3 changes in accordance with fluctuations in output potential VDD2, is formed. At this time, only a resistance component of the PMOS transistor Q3 exists and no differential amplifier is provided, on a path of current flowing-into the capacitor C1 (between the potential VCC and a low voltage side terminal C1N of the boosting capacitor).

Abstract: A semiconductor integrated circuit has complementary field-effect transistors, one formed in a semiconductor substrate, the other formed in a well in the substrate, and has four power-supply potentials: two supplied to the sources of the field-effect transistors, one supplied to the substrate, and one supplied to the well. An unwanted pair of parasitic bipolar transistors are formed in association with the field-effect transistors. An intentionally formed bipolar transistor operates in series with one of the unwanted parasitic transistors and as a current mirror for the other unwanted parasitic transistor, limiting the flow of unwanted current through the parasitic bipolar transistors.

Abstract: A driving circuit of a display device is provided. In a first time period of a data writing period, a control section of the driving circuit effects control so as to short-circuit a first node which is set to a target gradation potential and a node (second node) adjacent to the first node, and such that a line (second line) between the second node and a hold capacitor of a pixel is connected in parallel to a line (first line) between the first node and the hold capacitor of the pixel. Further, in a second time period following the first time period, the control section controls switching element groups so as to cancel short-circuiting between the first node and the second node, and such that the second line is not connected in parallel to the first line.

Abstract: The present invention provides a charge-pump boosting circuit. In a charging period of a capacitor C1, a PMOS transistor Q1 and an NMOS transistor Q2 turn on, and the capacitor C1 is charged by voltage between a potential VCC and a potential VSS. On the other hand, in a discharging period of a boosting capacitor, a PMOS transistor Q3 and a PMOS transistor Q4 turn on, and charges accumulated in the boosting capacitor are discharged. In a discharging period of the capacitor C1, a selector SEL1 selects a terminal T1, and a feedback system, in which operation voltage applied to a gate of the PMOS transistor Q3 changes in accordance with fluctuations in output potential VDD2, is formed. At this time, only a resistance component of the PMOS transistor Q3 exists and no differential amplifier is provided, on a path of current flowing-into the capacitor C1 (between the potential VCC and a low voltage side terminal C1N of the boosting capacitor).

Abstract: A semiconductor integrated circuit has complementary field-effect transistors, one formed in a semiconductor substrate, the other formed in a well in the substrate, and has four power-supply potentials: two supplied to the sources of the field-effect transistors, one supplied to the substrate, and one supplied to the well. An unwanted pair of parasitic bipolar transistors are formed in association with the field-effect transistors. An intentionally formed bipolar transistor operates in series with one of the unwanted parasitic transistors and as a current mirror for the other unwanted parasitic transistor, limiting the flow of unwanted current through the parasitic bipolar transistors.

Abstract: A CR oscillation circuit includes an oscillation unit having first through third invertion circuits connected in series between a first node and a second node, a capacitance element provided between the first node and an output terminal of the second inverting circuit, and a switch part for electrically connecting the first and second nodes according to a level of a control voltage; a constant current unit for allowing a constant current to flow according to a resistance value of an externally-provided resistive element to thereby supply a constant voltage; and a level conversion unit for converting a level of the constant voltage to thereby produce the control voltage.

Abstract: A semiconductor device includes a semiconductor substrate and an internal circuitry which is formed on the semiconductor substrate and which executes a predetermined operation. The device also includes a terminal which is connected to the internal circuitry and which receives an external signal and a protection circuitry which is formed on the semiconductor substrate. The protection circuitry includes a transistor having a first region of a first conductivity type, a second region of the first conductivity type and a third region of a second conductivity type. The first region is connected to the terminal. The second region is provided at a scribe line of the semiconductor substrate. The third region is defined by a region between the first region and the second region.

Abstract: A CR oscillation circuit includes an oscillation unit having first through third invertion circuits connected in series between a first node and a second node, a capacitance element provided between the first node and an output terminal of the second inverting circuit, and a switch part for electrically connecting the first and second nodes according to a level of a control voltage; a constant current unit for allowing a constant current to flow according to a resistance value of an externally-provided resistive element to thereby supply a constant voltage; and a level conversion unit for converting a level of the constant voltage to thereby produce the control voltage.

Abstract: A semiconductor device includes a semiconductor substrate and an internal circuitry which is formed on the semiconductor substrate and which executes a predetermined operation. The device also includes a terminal which is connected to the internal circuitry and which receives an external signal and a protection circuitry which is formed on the semiconductor substrate. The protection circuitry includes a transistor having a first region of a first conductivity type, a second region of the first conductivity type and a third region of a second conductivity type. The first region is connected to the terminal. The second region is provided at a scribe line of the semiconductor substrate. The third region is defined by a region between the first region and the second region.