Abstract: In a microwave plasma etching apparatus wherein the surface of a sample is exposed to a plasma generated by microwave discharge, thereby to subject the sample surface to an etching processing; the sample is transported while revolving along a circular orbit in a plasma exposure region, and the section of the plasma exposure region is put into the shape of a fan whose pivot coincides with the central point of the circuit orbit, whereby the enhancement of the etching processing capability and the uniformity of the etching speed are achieved.

Abstract: A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an insulating layer for insulating the first electrode is formed on the first electrode, and a first opening is provided in a part of this insulating layer.Subsequently, a second semiconductor circuit element is formed by forming a second electrode overlaying in part the insulating layer at an area other than the first opening and, a subsidiary conductive layer is formed in the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third openings are respectively provided in this latter insulating layer.First and second conductors are respectively deposited in the second and third openings, whereby electrical contact to the first and second electrodes are provided, with contact to the first electrode being via the subsidiary conductive layer.

Abstract: Micro-wave plasma etching is carried out with a gas containing at least SF.sub.6 as an etching gas at a high etching rate of silicon, and a high selectivity, with an easy monitoring and a low temperature dependency.

Abstract: A dry etching apparatus using microwaves according to the present invention is equipped with means for impressing such an AC voltage upon a sample as has a frequency ranging from 100 KHx to 10 MHx. Consequently, the sample has its surface prevented from being charged up no matter which it might be made of an insulator or might have its surface covered with an insulator. As a result, the etching rate can be maintained at a high level even for such sample.

Abstract: A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an inter-layer insulating layer for insulating the first electrode is formed on the first electrode, and a first penetrating opening is provided in a part of the inter-layer insulating layer.Subsequently, a step of forming a second semiconductor circuit element is carried out, this step including a step of forming a second electrode so that at least a part thereof may overlie the inter-layer insulating layer at an area other than the first penetrating opening. Further, a subsidiary interconnection conductive layer is buried into the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third penetrating openings are respectively provided in the insulating layer over the second electrode and the interconnection subsidiary conductive layer.First and second interconnection conductors are respectively buried into the second and third penetrating openings.

Abstract: An insulated gate field effect transistor formed on one main surface of a semiconductor substrate comprises a drain region the impurity concentration of which is lower than twice that of the semiconductor substrate and the conductivity type is reverse to that of the substrate and a region of a high impurity concentration, formed in the low impurity concentration region, the conductivity type of which is the same as that of the low impurity concentration region.