Patents by Inventor Shigeru Sugino
Shigeru Sugino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10863629Abstract: A method of manufacturing a through hole of a substrate includes forming, to the substrate, a cutting hole surrounding a removal-target-part such that a connection part of the substrate remains, the connection part that connects the removal-target-part that is removed from the substrate and a remaining part other than the removal-target-part that has been removed, along a cutting line of the through hole formed to the substrate; applying plating on an area including an inner peripheral wall face of the cutting hole of the substrate; applying a film covering an opening of the cutting hole on a surface of the substrate applied with the plating and performing exposure and development of the film to form an etching resist covering an area including the opening of the cutting hole; performing etching of the plating applied on the substrate; removing the etching resist; and cutting the connection part to remove the removal-target-part.Type: GrantFiled: July 17, 2019Date of Patent: December 8, 2020Assignee: FUJITSU LIMITEDInventors: Kiyoyuki Hatanaka, Shigeru Sugino, Takahiro Kitagawa, Ryo Kanai, Nobuo Taketomi, Mitsunori Abe
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Patent number: 10624216Abstract: A wiring board includes, a base plate that has a first surface, a second surface opposite to the first surface, and a side surface coupled to the first surface and the second surface, a conductor provided on the side surface, and a protrusion provided over the side surface. The protrusion partitions the conductor into a first portion on the side surface that extends to the first surface and a second portion on the side surface that extends to the second surface. The protrusion has a solder wettability lower than the conductor and protrudes from the conductor.Type: GrantFiled: October 3, 2018Date of Patent: April 14, 2020Assignee: FUJITSU LIMITEDInventors: Nobuo Taketomi, Takahiro Kitagawa, Mitsunori Abe, Shigeru Sugino, Kiyoyuki Hatanaka, Shigeo Iriguchi, Ryo Kanai
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Patent number: 10605851Abstract: A printed wiring board includes: a laminated body that has a plurality of wiring layers laminated therein; a first through hole that electrically connects two or more wiring layers with each other; and a second through hole that has strength to expansion and contraction of the laminated body less than in the first through hole.Type: GrantFiled: June 16, 2017Date of Patent: March 31, 2020Assignee: FUJITSU LIMITEDInventors: Shigeo Iriguchi, Naoki Nakamura, Shigeru Sugino, Takahide Mukoyama, Ryo Kanai, Nobuo Taketomi, Kiyoyuki Hatanaka
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Publication number: 20200037452Abstract: A method of manufacturing a through hole of a substrate includes forming, to the substrate, a cutting hole surrounding a removal-target-part such that a connection part of the substrate remains, the connection part that connects the removal-target-part that is removed from the substrate and a remaining part other than the removal-target-part that has been removed, along a cutting line of the through hole formed to the substrate; applying plating on an area including an inner peripheral wall face of the cutting hole of the substrate; applying a film covering an opening of the cutting hole on a surface of the substrate applied with the plating and performing exposure and development of the film to form an etching resist covering an area including the opening of the cutting hole; performing etching of the plating applied on the substrate; removing the etching resist; and cutting the connection part to remove the removal-target-part.Type: ApplicationFiled: July 17, 2019Publication date: January 30, 2020Applicant: FUJITSU LIMITEDInventors: Kiyoyuki Hatanaka, Shigeru Sugino, Takahiro Kitagawa, Ryo Kanai, Nobuo Taketomi, Mitsunori Abe
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Patent number: 10393797Abstract: A method for inspecting a laminated board, includes: performing a reflow process to solder an electronic component to a surface of a laminated board in which at least one of a plurality of wiring layers which are laminated with each other is coupled to another adjacent wiring layer via a via; and inspecting, in the reflow process, a conduction state of the via after a temperature of the laminated board reaches a melting point of a solder, and when the temperature of the laminated board is at a temperature range lower than the melting point and higher than room temperature.Type: GrantFiled: June 15, 2017Date of Patent: August 27, 2019Assignee: FUJITSU LIMITEDInventors: Mitsunori Abe, Takahiro Kitagawa, Shigeo Iriguchi, Kiyoyuki Hatanaka, Shigeru Sugino, Ryo Kanai
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Patent number: 10342129Abstract: A substrate includes an insulation layer including a glass cloth impregnated with a resin, and a through hole having a hole included in the insulation layer and plating formed in an inner surface of the hole, where a location, intersecting with the glass cloth, of an outer circumferential portion of the through hole has a recessed portion recessed toward an outside of the hole.Type: GrantFiled: April 5, 2018Date of Patent: July 2, 2019Assignee: FUJITSU LIMITEDInventors: Shigeo Iriguchi, Takahiro Kitagawa, Mitsunori Abe, Shigeru Sugino, Nobuo Taketomi, Kiyoyuki Hatanaka, Ryo Kanai
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Publication number: 20190110365Abstract: A wiring board includes, a base plate that has a first surface, a second surface opposite to the first surface, and a side surface coupled to the first surface and the second surface, a conductor provided on the side surface, and a protrusion provided over the side surface. The protrusion partitions the conductor into a first portion on the side surface that extends to the first surface and a second portion on the side surface that extends to the second surface. The protrusion has a solder wettability lower than the conductor and protrudes from the conductor.Type: ApplicationFiled: October 3, 2018Publication date: April 11, 2019Applicant: FUJITSU LIMITEDInventors: Nobuo Taketomi, Takahiro KITAGAWA, Mitsunori Abe, Shigeru SUGINO, Kiyoyuki Hatanaka, Shigeo Iriguchi, Ryo Kanai
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Publication number: 20180310405Abstract: A substrate includes an insulation layer including a glass cloth impregnated with a resin, and a through hole having a hole included in the insulation layer and plating formed in an inner surface of the hole, where a location, intersecting with the glass cloth, of an outer circumferential portion of the through hole has a recessed portion recessed toward an outside of the hole.Type: ApplicationFiled: April 5, 2018Publication date: October 25, 2018Applicant: FUJITSU LIMITEDInventors: Shigeo Iriguchi, Takahiro KITAGAWA, Mitsunori Abe, Shigeru SUGINO, Nobuo Taketomi, Kiyoyuki Hatanaka, Ryo Kanai
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Publication number: 20180059170Abstract: A method for inspecting a laminated board, includes: performing a reflow process to solder an electronic component to a surface of a laminated board in which at least one of a plurality of wiring layers which are laminated with each other is coupled to another adjacent wiring layer via a via; and inspecting, in the reflow process, a conduction state of the via after a temperature of the laminated board reaches a melting point of a solder, and when the temperature of the laminated board is at a temperature range lower than the melting point and higher than room temperature.Type: ApplicationFiled: June 15, 2017Publication date: March 1, 2018Applicant: FUJITSU LIMITEDInventors: Mitsunori ABE, Takahiro Kitagawa, Shigeo Iriguchi, Kiyoyuki Hatanaka, Shigeru Sugino, Ryo Kanai
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Publication number: 20170285096Abstract: A printed wiring board includes: a laminated body that has a plurality of wiring layers laminated therein; a first through hole that electrically connects two or more wiring layers with each other; and a second through hole that has strength to expansion and contraction of the laminated body less than in the first through hole.Type: ApplicationFiled: June 16, 2017Publication date: October 5, 2017Applicant: FUJITSU LIMITEDInventors: Shigeo IRIGUCHI, Naoki NAKAMURA, Shigeru SUGINO, Takahide MUKOYAMA, Ryo KANAI, Nobuo TAKETOMI, Kiyoyuki HATANAKA
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Patent number: 9709619Abstract: A printed wiring board includes: a laminated body that has a plurality of wiring layers laminated therein; a first through hole that electrically connects two or more wiring layers with each other; and a second through hole that has strength to expansion and contraction of the laminated body less than in the first through hole.Type: GrantFiled: July 15, 2013Date of Patent: July 18, 2017Assignee: FUJITSU LIMITEDInventors: Shigeo Iriguchi, Naoki Nakamura, Shigeru Sugino, Takahide Mukoyama, Ryo Kanai, Nobuo Taketomi, Kiyoyuki Hatanaka
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Patent number: 9295155Abstract: A flexible printed board includes a base material, first conductive pads arranged along an imaginary line on the base material and extending with a first width from front end to rear end on a front side of the imaginary line, second conductive pads arranged along the imaginary line and extending with a second width from front end on a rear side of the imaginary line to rear end, first wiring patterns provided between the second conductive pads, and extending with a third width to front end connected to the rear ends of the first conductive pads, and a reinforcing layer for reinforcing a reinforcing area over the first conductive pads and the first wiring patterns, and having a front edge on a front side of rear ends of the first conductive pads and a rear edge on a rear side of the rear ends of the second conductive pads.Type: GrantFiled: August 21, 2012Date of Patent: March 22, 2016Assignee: FUJITSU LIMITEDInventors: Naoki Nakamura, Shigeru Sugino, Nobuo Taketomi, Ryo Kanai
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Publication number: 20140077834Abstract: A printed wiring board includes: a laminated body that has a plurality of wiring layers laminated therein; a first through hole that electrically connects two or more wiring layers with each other; and a second through hole that has strength to expansion and contraction of the laminated body less than in the first through hole.Type: ApplicationFiled: July 15, 2013Publication date: March 20, 2014Inventors: Shigeo IRIGUCHI, Naoki NAKAMURA, Shigeru SUGINO, Takahide MUKOYAMA, Ryo KANAI, Nobuo TAKETOMI, Kiyoyuki HATANAKA
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Publication number: 20120312586Abstract: A flexible printed board includes a base material, first conductive pads arranged along an imaginary line on the base material and extending with a first width from front end to rear end on a front side of the imaginary line, second conductive pads arranged along the imaginary line and extending with a second width from front end on a rear side of the imaginary line to rear end, first wiring patterns provided between the second conductive pads, and extending with a third width to front end connected to the rear ends of the first conductive pads, and a reinforcing layer for reinforcing a reinforcing area over the first conductive pads and the first wiring patterns, and having a front edge on a front side of rear ends of the first conductive pads and a rear edge on a rear side of the rear ends of the second conductive pads.Type: ApplicationFiled: August 21, 2012Publication date: December 13, 2012Applicant: FUJITSU LIMITEDInventors: Naoki Nakamura, Shigeru Sugino, Nobuo Taketomi, Ryo Kanai
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Patent number: 8305767Abstract: Terminal pads are arranged on a first surface of the substrate for an electronic component to receive terminals of the electronic component. An electrically-conductive film is formed on a second surface defined on the back of the first surface over the back of a mounting area for the electronic component. The mounting area is contoured along the outer periphery of the arrangement of the terminal pads. The ratio of the area of the electrically-conductive material to the area of the surface of the substrate over the back of the mounting area is set appropriate to the ratio of the area of the electrically-conductive material to the area of the surface of the substrate over the mounting area for each electronic component. This results in suppression of flexure of the printed wiring board during reflow.Type: GrantFiled: September 28, 2007Date of Patent: November 6, 2012Assignee: Fujitsu LimitedInventors: Naoki Nakamura, Shigeru Sugino, Ryo Kanai
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Patent number: 8269114Abstract: A flexible printed board includes a base material, first conductive pads arranged along an imaginary line on the base material and extending with a first width from front end to rear end on a front side of the imaginary line, second conductive pads arranged along the imaginary line and extending with a second width from front end on a rear side of the imaginary line to rear end, first wiring patterns provided between the second conductive pads, and extending with a third width to front end connected to the rear ends of the first conductive pads, and a reinforcing layer for reinforcing a reinforcing area over the first conductive pads and the first wiring patterns, and having a front edge on a front side of rear ends of the first conductive pads and a rear edge on a rear side of the rear ends of the second conductive pads.Type: GrantFiled: February 2, 2010Date of Patent: September 18, 2012Assignee: Fujitsu LimitedInventors: Naoki Nakamura, Shigeru Sugino, Nobuo Taketomi, Ryo Kanai
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Patent number: 8233286Abstract: Terminal pads are arranged on a first surface of the substrate for an electronic component to receive terminals of the electronic component. An electrically-conductive film is formed on a second surface defined on the back of the first surface over the back of a mounting area for the electronic component. The mounting area is contoured along the outer periphery of the arrangement of the terminal pads. The ratio of the area of the electrically-conductive material to the area of the surface of the substrate over the back of the mounting area is set appropriate to the ratio of the area of the electrically-conductive material to the area of the surface of the substrate over the mounting area for each electronic component. This results in suppression of flexure of the printed wiring board during reflow.Type: GrantFiled: September 28, 2007Date of Patent: July 31, 2012Assignee: Fujitsu LimitedInventors: Naoki Nakamura, Shigeru Sugino, Ryo Kanai
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Publication number: 20110286188Abstract: A multilayer printed circuit board includes an interior interconnect layer, and a semiconductor package including a flexible interconnect structure whose distal end is a free end, wherein the flexible interconnect structure and the interior interconnect layer are electrically connected to each other.Type: ApplicationFiled: March 15, 2011Publication date: November 24, 2011Applicant: FUJITSU LIMITEDInventors: Ryo KANAI, Shunichi KIKUCHI, Naoki NAKAMURA, Shigeru SUGINO, Kiyoyuki HATANAKA, Nobuo TAKETOMI
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Patent number: 8035978Abstract: A printed circuit board includes a mounted a first electronic component. The printed circuit board includes a first through holes extending from a mounting surface on which the electronic component is mounted. The printed circuit board includes a second through holes extending from a surface opposite the mounting surface and aligned with the first through holes. A second electronic component may be longitudinally between the first through holes and the second through holes. The first and second through holes may be electrically connected with the second electronic component.Type: GrantFiled: August 27, 2008Date of Patent: October 11, 2011Assignee: Fujitsu LimitedInventor: Shigeru Sugino
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Publication number: 20110132654Abstract: A method for manufacturing a multilayer printed circuit board, and a printed circuit board manufactured according to the method, includes laterally-aligning a first inner substrate in which first insulation layers and first conductor layers are alternately laminated and a second inner substrate in which second insulation layers and second conductor layers are alternately laminated. The second inner substrate has a lager number of layers than the first inner substrate. The laterally-aligned first inner substrate and second inner substrate are placed between a pair of third insulation layers in a thickness direction. The pair of the third insulation layer are heated under pressure in the thickness direction. A conductor pattern is formed on surfaces of the pair of the third insulation layers.Type: ApplicationFiled: December 3, 2010Publication date: June 9, 2011Applicant: FUJITSU LIMITEDInventors: Nobuo TAKETOMI, Shunichi KIKUCHI, Naoki NAKAMURA, Kiyoyuki HATANAKA, Shigeru SUGINO, Ryo KANAI