Patents by Inventor Shigeru Takahashi
Shigeru Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6153822Abstract: A musical apparatus which controls a variety of parameters of musical tones by detecting motion of an object in a space adjacent to the musical apparatus. More specifically, the musical apparatus may comprise a musical tone signal generator which generates a musical tone signal, at least one light source which radiates light beams into a space adjacent to the musical apparatus, at least one light detector which detects at least two light beams reflected from an object in the space and generates a detection value for each of said at least two light beams, a computing element which receives the detection values and generates a synthesized value; and a controller which controls parameters of musical tones based on the synthesized value. For example, the synthesized value may be the sum of the detection values, the difference between the detection values, the ratio between the detection values, or some other relationship between the detection values.Type: GrantFiled: October 20, 1999Date of Patent: November 28, 2000Assignee: Roland Kabushiki KaishaInventors: Yoshihiro Toba, Shigeru Takahashi
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Patent number: 6111182Abstract: A system for editing and reproducing sounds according to pre-stored waveform data and recorded waveform data is disclosed. Pre-stored waveform data including timing information and musical tones are stored in memory. Musical tone waveform data including timing information from external sources such as electronic musical instruments, non-electronic musical instruments, and voices can also be stored in memory. The waveform data stored in memory can be edited before it is sequentially read out and a musical tone signal is reproduced.Type: GrantFiled: January 27, 1999Date of Patent: August 29, 2000Assignee: Roland CorporationInventor: Shigeru Takahashi
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Patent number: 6076242Abstract: A cut pile fabric with substantially vertically standing tufts made of a synthetic multifilament yarn which is an intermingled yarn comprised of (a) a crimped multifilament yarn and (b) a non-crimped highly heat-shrinkable multifilament yarn having a heat shrinkage larger than that of the crimped multifilament yarn (a), and having thick portions and thin portions, alternately occurring along the length of each constituting filament of the yarn (b), said thick portions having a heat shrinkage larger than that of said thin portions. When heat-treated, the cut pile fabric provides a high-and-low cut pile fabric having a unique appearance. Especially when tip portions of cut piles of the crimped multifilament yarn (a) are entangled with each other, a cut pile fabric having a rugged surface with lumps of snarled piles is obtained.Type: GrantFiled: August 13, 1998Date of Patent: June 20, 2000Assignee: Teijin LimitedInventors: Katsuyuki Kasaoka, Shigeru Takahashi, Mitsuo Matsumoto, Akio Kimura
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Patent number: 6022797Abstract: First through holes of a relatively small diameter and second through holes of a relatively great diameter are formed in proper shapes by separate processes, respectively, in a first layer insulating film. The second through holes are tapered toward a layer underlying the first layer insulating film. First, the first through holes are formed in the first layer insulating film, the first through holes are filled up with plug electrodes, and the second through holes are formed in the first layer insulating film. When filling up the first and the second through holes formed in the first layer insulating film with plug electrodes, a first conductive film deposited over the first layer insulating film is etched back to fill up the first through holes with the plug electrodes, and then etch back residues remaining on the side walls of the second through holes are removed.Type: GrantFiled: November 24, 1997Date of Patent: February 8, 2000Assignee: Hitachi, Ltd.Inventors: Shigeo Ogasawara, Shigeru Takahashi, Noriaki Oka, Tadayasu Miki, Masahito Hiroshima
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Patent number: 5998727Abstract: A musical apparatus which controls a variety of parameters of musical tones by detecting motion of an object in a space adjacent to the musical apparatus. More specifically, the musical apparatus may comprise a musical tone signal generator which generates a musical tone signal, at least one light source which radiates light beams into a space adjacent to the musical apparatus, at least one light detector which detects at least two light beams reflected from an object in the space and generates a detection value for each of said at least two light beams, a computing element which receives the detection values and generates a synthesized value; and a controller which controls parameters of musical tones based on the synthesized value. For example, the synthesized value may be the sum of the detection values, the difference between the detection values, the ratio between the detection values, or some other relationship between the detection values.Type: GrantFiled: December 10, 1998Date of Patent: December 7, 1999Assignee: Roland Kabushiki KaishaInventors: Yoshihiro Toba, Shigeru Takahashi
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Patent number: 5990409Abstract: A musical apparatus which outputs music under the control of various musical control instructions where the desired musical control instructions are reliably determined by the movement of an object in an operation space, and where the musical control instructions are varied by changing the state of motion of the object in space.The musical apparatus performs musical control instructions whose contents are based on the state of motion of an object in motion within a specified operation space.Type: GrantFiled: December 22, 1998Date of Patent: November 23, 1999Assignee: Roland Kabushiki KaishaInventors: Shigeru Takahashi, Akira Matsui
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Patent number: 5986294Abstract: A semiconductor integrated circuit having three or more layers of wiring is provided with a plurality of lines of bonding pads arranged along the outer peripheral portion of a semiconductor chip. The bonding pads on the inner line side and those on the outer line side are arranged in a zigzag manner. First outgoing wiring for electrically connecting the bonding pads on the inner line side and internal circuits (input/output buffer circuits) is formed in one layer of wiring or a plurality of layers of wiring including at least the uppermost layer of wiring, and second outgoing wiring for electrically connecting the bonding pads on the outer line side and the internal circuits (the input/output buffer circuits) is formed in a plurality of layers of wiring other than the layer in which the first outgoing wiring is formed.Type: GrantFiled: January 7, 1999Date of Patent: November 16, 1999Assignee: Hitachi, Ltd.Inventors: Tadayasu Miki, Shigeo Ogasawara, Noriaki Oka, Shigeru Takahashi, Mitsuaki Katagiri
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Patent number: 5936327Abstract: In an electro-mechanical energy conversion device which is disclosed, green sheets on which whole surface electrodes for grounding have been printed and green sheets on which 2-divided electrodes have been printed are laminated. The green sheets having the 0.degree. phase and 90.degree. phase on which the 2-divided electrodes have been printed are laminated through the printed sheet on which the whole surface electrode for grounding. After the laminate body was sintered and integrated, it is polarized in a manner such that the polarizing directions in the thickness direction of each layer are opposite between the two divided electrodes which form one pair by using the whole surface electrodes for grounding and the 2-divided electrodes which were printed, thereby constructing the conversion device for the laminated type vibration driven motor.Type: GrantFiled: September 2, 1997Date of Patent: August 10, 1999Assignees: Canon Kabushiki Kaisha, Taiheiyo Cement CorporationInventors: Shigeru Takahashi, Sadakatsu Okura, Toshikatsu Nomura
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Patent number: 5892276Abstract: A semiconductor integrated circuit having three or more layers of wiring is provided with a plurality of lines of bonding pads arranged along the outer peripheral portion of a semiconductor chip. The bonding pads on the inner line side and those on the outer line side are arranged in a zigzag manner. First outgoing wiring for electrically connecting the bonding pads on the inner line side and internal circuits (input/output buffer circuits) is formed in one layer of wiring or a plurality of layers of wiring including at least the uppermost layer of wiring, and second outgoing wiring for electrically connecting the bonding pads on the outer line side and the internal circuits (the input/output buffer circuits) is formed in a plurality of layers of wiring other than the layer in which the first outgoing wiring is formed.Type: GrantFiled: April 17, 1997Date of Patent: April 6, 1999Assignee: Hitachi, Ltd.Inventors: Tadayasu Miki, Shigeo Ogasawara, Noriaki Oka, Shigeru Takahashi, Mitsuaki Katagiri
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Patent number: 5834851Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.Type: GrantFiled: June 2, 1995Date of Patent: November 10, 1998Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake
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Patent number: 5819163Abstract: A portable remote terminal includes a case, and a remote terminal body assembly into which at least a printed-circuit board having electric circuits required for the portable remote terminal and a loudspeaker electrically connected to the printed-circuit board are assembled, the remote terminal body assembly being housed in the case.Type: GrantFiled: September 6, 1996Date of Patent: October 6, 1998Assignee: Fujitsu LimitedInventors: Yoshifumi Tsukamoto, Shigeru Takahashi, Yoshiaki Katou, Hisamitsu Takagi
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Patent number: 5787043Abstract: A semiconductor device is provided which comprises a memory mat formed by dividing a memory into a plurality of blocks and a circuit arrangement disposed at every memory mat block for generating access suppression signals at least for defective memory cells within that block. Using this arrangement, the access speed to a redundant memory cell array for relieving the defects is increased so that a semiconductor memory device capable of a high speed operation is obtained.Type: GrantFiled: February 27, 1995Date of Patent: July 28, 1998Assignee: Hitachi, Ltd.Inventors: Takashi Akioka, Yuji Yokoyama, Atsushi Hiraishi, Masahiro Iwamura, Yutaka Kobayashi, Tatsumi Yamauchi, Shigeru Takahashi, Koichi Motohashi
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Patent number: 5767554Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.Type: GrantFiled: June 2, 1995Date of Patent: June 16, 1998Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake
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Patent number: 5731219Abstract: Herein disclosed is a semiconductor integrated circuit device comprising an SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs, and a method of forming this device. The gate electrodes of the drive MISFETs and of the transfer MISFETs of the memory cell, and the word lines, are individually formed of different conductive layers. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The source line is formed of a conductive layer identical to that of the word line. An oxidation resisting film is formed on the gate electrodes of the drive MISFETs so as to reduce stress caused by oxidization of edge portions of these gate electrodes, and to reduce a resulting leakage current.Type: GrantFiled: June 2, 1995Date of Patent: March 24, 1998Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake
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Patent number: 5700704Abstract: A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.Type: GrantFiled: June 2, 1995Date of Patent: December 23, 1997Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake
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Patent number: 5675548Abstract: An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.Type: GrantFiled: February 29, 1996Date of Patent: October 7, 1997Assignee: Hitachi, Ltd.Inventors: Yuji Yokoyama, Takashi Akioka, Masahiro Iwamura, Atsushi Hiraishi, Yutaka Kobayashi, Tatsumi Yamauchi, Shigeru Takahashi, Nobuyuki Gotou, Akira Ide
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Method of manufacturing an electro-mechanical energy conversion device for vibration driven actuator
Patent number: 5669127Abstract: In an electro-mechanical energy conversion device which is disclosed, green sheets on which whole surface electrodes for grounding have been printed and green sheets on which 2-divided electrodes have been printed are laminated. The green sheets having the 0.degree. phase and 90.degree. phase on which the 2-divided electrodes have been printed are laminated through the printed sheet on which the whole surface electrode for grounding. After the laminate body was sintered and integrated, it is polarized in a manner such that the polarizing directions in the thickness direction of each layer are opposite between the two divided electrodes which form one pair by using the whole surface electrodes for grounding and the 2-divided electrodes which were printed, thereby constructing the conversion device for the laminated type vibration driven motor.Type: GrantFiled: November 5, 1996Date of Patent: September 23, 1997Assignees: Canon Kabushiki Kaisha, Nihon Cement Co, Ltd.Inventors: Shigeru Takahashi, Sadakatsu Okura, Toshikatsu Nomura -
Patent number: 5656836Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected-with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.Type: GrantFiled: June 2, 1995Date of Patent: August 12, 1997Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake
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Patent number: 5652457Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.Type: GrantFiled: November 30, 1994Date of Patent: July 29, 1997Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake
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Patent number: 5636275Abstract: A hinge mechanism for use in a portable telephone in which a foldable lid is rotatably supported by the hinge mechanism to rotate the foldable lid between an opened position and a closed position, includes a rotary shaft on which the lid is rotatably supported. A first spring, fitted to the shaft, generates a biasing force to rotate the lid on the shaft in a first direction from the closed position to the opened position. A second spring, fitted to the shaft, generates a biasing force to rotate the lid on the shaft in a second direction opposite to the first direction after the lid is further rotated from the opened position in the first direction. A first stopper restricts a rotation of the shaft in the first direction to cancel the biasing force of the first spring when the lid is further rotated on the shaft in the first direction from the opened position.Type: GrantFiled: February 6, 1996Date of Patent: June 3, 1997Assignee: Fujitsu LimitedInventors: Hisamitsu Takagi, Takahiro Agai, Tatsuzi Shigeta, Shigeru Takahashi, Yosiaki Kato