Abstract: A module includes: a resin insulating layer; a first electronic component mounted on a lower surface of the resin insulating layer and including first and second terminals on an upper surface of the first electronic component; a resin bonding layer bonding the lower surface of the resin insulating layer to the upper surface of the first electronic component; first and second wiring lines located on inner surfaces of at least one first through hole and at least one second through hole penetrating through the resin insulating layer and the resin bonding layer, respectively, located on an upper surface of the resin insulating layer, and connecting to the first and second terminals, respectively, wherein an opening penetrating through the resin insulating layer and the resin bonding layer is provided between the first and second terminals and between the first and second wiring lines, and no other metal layers are provided.

Abstract: A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an alignment post electrode which is formed in the alignment mark formation region and smaller in number than the post electrodes formed in each semiconductor device formation region.

Abstract: A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an alignment post electrode which is formed in the alignment mark formation region and smaller in number than the post electrodes formed in each semiconductor device formation region.

Abstract: A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an alignment post electrode which is formed in the alignment mark formation region and smaller in number than the post electrodes formed in each semiconductor device formation region.

Abstract: A formed building material is provided of which front surface is allowed to be glazed, thereby improving its decorative property and improving its soil resistance and which has hazardous substance adsorbing function. This formed building material is produced by baking, a glaze is applied to a front surface of a main body of the formed building material, and the specific surface area of the main body is 10 m2/g or more. The main body has porosity of 20-50%, and more than 40% of pores of the main body have a radius of less than 0.1 &mgr;m. The glaze forms a glass layer on 90% or less of the entire surface area of the main body and/or the maximum thickness of the glass layer formed by the glaze is 300 &mgr;m or less. The formed building material is attached to a lower portion of a wall and/or a floor of a room.

Abstract: A grinding machine includes a main spindle on which a grinding wheel is mounted, a spindle head movable relative to a workpiece, a dressing device body provided to be movable relative to the spindle head and a dresser supporting member provided to be movable relative to the dressing device body for rotatably supporting a dresser. The dressing device body is moved to a dressing position while the grinding machine grinds with continuous dressing. The dressing device body is moved to a retracted position while the grinding machine normally grinds except for the grinding with continuous dressing.

Abstract: A bump electrode structure of a semiconductor device comprises an electrode pad formed of an aluminum alloy, an insulating oxide layer covering only the peripheral edge portion of the electrode pad, an under-bump layer formed of an alloy of titanium and tungsten, and a bump electrode formed of gold. The titanium-tungsten alloy functions both as a barrier metal and as a bonding metal. The bump electrode rises substantially straight from the bonding surface of the under-bump layer, and its top portion has an area only substantially equal to that of the electrode pad. Fine V-shaped grooves are formed on the top surface of the bump electrode by anisotropic etching. Thus, the semiconductor device with fine electrode pad pitches is provided with a high-reliability bump electrode structure which ensures sufficient bonding strength between internal and external electrodes.