Patents by Inventor Shigeto OSHINO
Shigeto OSHINO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8895952Abstract: A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.Type: GrantFiled: February 24, 2012Date of Patent: November 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shigeki Kobayashi, Kazuhiko Yamamoto, Kenji Aoyama, Shigeto Oshino, Kei Watanabe, Shinichi Nakao, Satoshi Ishikawa, Takeshi Yamaguchi
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Patent number: 8765565Abstract: According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide.Type: GrantFiled: July 9, 2013Date of Patent: July 1, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Aoyama, Kazuhiko Yamamoto, Satoshi Ishikawa, Shigeto Oshino
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Publication number: 20140147942Abstract: According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.Type: ApplicationFiled: February 4, 2014Publication date: May 29, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kenji AOYAMA, Kazuhiko YAMAMOTO, Satoshi ISHIKAWA, Shigeto OSHINO
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Patent number: 8716691Abstract: According to one embodiment, a nonvolatile memory device includes a lower electrode layer, a nanomaterial assembly layer, and an upper electrode layer. The nanomaterial assembly layer is provided on the lower electrode layer and includes a plurality of micro conductive bodies assembled via a gap. The upper electrode layer is provided on the nanomaterial assembly layer. The portion of the micro conductive bodies is buried at least in a lower part of the upper electrode layer.Type: GrantFiled: December 20, 2010Date of Patent: May 6, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Shigeto Oshino
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Patent number: 8686384Abstract: According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.Type: GrantFiled: March 21, 2011Date of Patent: April 1, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kenji A{dot over (o)}yama, Kazuhiko Yamamoto, Satoshi Ishikawa, Shigeto Oshino
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Publication number: 20130295743Abstract: According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide.Type: ApplicationFiled: July 9, 2013Publication date: November 7, 2013Inventors: Kenji AOYAMA, Kazuhiko YAMAMOTO, Satoshi ISHIKAWA, Shigeto OSHINO
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Patent number: 8507888Abstract: According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide.Type: GrantFiled: February 1, 2011Date of Patent: August 13, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Aoyama, Kazuhiko Yamamoto, Satoshi Ishikawa, Shigeto Oshino
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Publication number: 20120217464Abstract: A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.Type: ApplicationFiled: February 24, 2012Publication date: August 30, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Shigeki Kobayashi, Kazuhiko Yamamoto, Kenji Aoyama, Shigeto Oshino, Kei Watanabe, Shinichi Nakao, Satoshi Ishikawa, Takeshi Yamaguchi
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Publication number: 20120205609Abstract: According to one embodiment, a memory device includes a lower electrode layer, a nanomaterial assembly layer, a protective layer and an upper electrode layer. The nanomaterial assembly layer is provided on the lower electrode layer and includes a plurality of fine conductors assembled via a gap. The protective layer is provided on the nanomaterial assembly layer, is conductive, is in contact with the fine conductors, and includes an opening. The upper electrode layer is provided on the protective layer and is in contact with the protective layer.Type: ApplicationFiled: September 19, 2011Publication date: August 16, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigeto OSHINO, Kenji Aoyama, Kazuhiko Yamamoto, Shinichi Nakao, Kei Watanabe, Satoshi Ishikawa
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Publication number: 20120104352Abstract: According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.Type: ApplicationFiled: March 21, 2011Publication date: May 3, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Kenji AOYAMA, Kazuhiko Yamamoto, Satoshi Ishikawa, Shigeto Oshino
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Publication number: 20120056145Abstract: According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide.Type: ApplicationFiled: February 1, 2011Publication date: March 8, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenji AOYAMA, Kazuhiko Yamamoto, Satoshi Ishikawa, Shigeto Oshino
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Publication number: 20120012803Abstract: According to one embodiment, a nonvolatile memory device includes a lower electrode layer, a nanomaterial assembly layer, and an upper electrode layer. The nanomaterial assembly layer is provided on the lower electrode layer and includes a plurality of micro conductive bodies assembled via a gap. The upper electrode layer is provided on the nanomaterial assembly layer. The portion of the micro conductive bodies is buried at least in a lower part of the upper electrode layer.Type: ApplicationFiled: December 20, 2010Publication date: January 19, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Shigeto OSHINO