Patents by Inventor Shigetoshi Nohda

Shigetoshi Nohda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6295087
    Abstract: The present invention enables to obtain an image of a high resolution as reasonable costs by using an adaptive interpolation circuit which is supplied by image data R, G, and B which have been subjected to a white balance adjustment in a DSP and an R-G image is combined in an internal memory. The adaptive interpolation circuit calculates correlation degrees in a vertical direction, a horizontal direction, and diagonal directions. If an interpolation is executed according to the R-G image in the direction having the greatest correlation degree, no LPF processing is executed, i.e., no resolution deterioration is caused in a direction which orthogonally intersects the aforementioned direction. That is, the adaptive interpolation circuit enables to enhance a resolution by executing an interpolation according to the correlation of the image data around a portion to be interpolated.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: September 25, 2001
    Assignee: Sony Corporation
    Inventor: Shigetoshi Nohda
  • Patent number: 6215875
    Abstract: A cipher processing apparatus which readily updates a cipher processing circuit for encrypting information communicated through a communication function. A service station side and a user side are connected. A receiving function receives a command for requesting a change of a cipher processing program and the cipher processing program which are transmitted from the service station side to the user side through the communication function. Circuit updating function updates a cipher processing circuit provided on the user side with the cipher processing program. With these functions, the cipher processing circuit provided on the user side can be readily rewritten in accordance with the cipher processing program transmitted from the service station side.
    Type: Grant
    Filed: January 12, 1998
    Date of Patent: April 10, 2001
    Assignee: Sony Corporation
    Inventor: Shigetoshi Nohda
  • Patent number: 5986715
    Abstract: (M-N) 0 data are inserted for every N data of the f.sub.SL input data by an interpolation circuit 20 for generating f.sub.SH rate data, while filter coefficients are sequentially generated by M coefficient generators 30A to 30D at the f.sub.SH rate. A register postfix type transversal filter 40 effectuates up rate conversion of N:M (N<M) of generating f.sub.SH rate output data from f.sub.SL rate input data. The transversal filter 40 includes M multipliers 41A to 41D for multiplying the f.sub.SH rate data generated by the interpolation circuit 20 with the filter coefficients sequentially applied by the coefficient generators 30A to 30D and each (M-1) delay circuits 42A to 42C and additive units 43A to 43C for delaying product outputs of the multipliers 41A to 41D by unit time delay and summing the delayed product output together.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: November 16, 1999
    Assignee: Sony Corporation
    Inventors: Hiromasa Ikeyama, Taku Kihara, Shigetoshi Nohda
  • Patent number: 5680335
    Abstract: (M-N) 0 data are inserted for every N data of the f.sub.SL input data by an interpolation circuit 20 for generating f.sub.SH rate data, while filter coefficients are sequentially generated by M coefficient generators 30A to 30D at the f.sub.SH rate. A register postfix type transversal filter 40 effectuates up rate conversion of N:M (N<M) of generating f.sub.SH rate output data from f.sub.SL rate input data. The transversal filter 40 includes M multipliers 41A to 41D for multiplying the f.sub.SH rate data generated by the interpolation circuit 20 with the filter coefficients sequentially applied by the coefficient generators 30A to 30D and each (M-1) delay circuits 42A to 42C and additive units 43A to 43C for delaying product outputs of the multipliers 41A to 41D by unit time delay and summing the delayed product output together.
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: October 21, 1997
    Assignee: Sony Corporation
    Inventors: Hiromasa Ikeyama, Taku Kihara, Shigetoshi Nohda
  • Patent number: 5369266
    Abstract: A solid-state image pickup device for imaging an object using a CCD image sensor. The solid-state image pickup device includes a half wave plate between first and second birefringence plates 2 and 4 shifting the optical path of the image pickup light the radiation of which is interrupted by on/off control of an electrical voltage. The half wave plate transforms an ordinary light ray into an extraordinary light ray and radiates the resulting extraordinary light ray, while transforming an extraordinary light ray into an ordinary light ray and radiates the resulting ordinary light ray. The image pickup light is radiated to the CCD image sensor while the voltage to be applied across the first and second birefringence plates is on/off controlled simultaneously. When the voltage to be applied across the first and the second birefringence plates is turned off, the image pickup light ray is radiated to the CCD image sensor as an extraordinary light ray without its optical path being changed.
    Type: Grant
    Filed: June 10, 1993
    Date of Patent: November 29, 1994
    Assignee: Sony Corporation
    Inventors: Shigetoshi Nohda, Kakuji Kunii