Patents by Inventor Shigetoshi Sakomura

Shigetoshi Sakomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor
    Patent number: 5805513
    Abstract: A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
    Type: Grant
    Filed: May 2, 1995
    Date of Patent: September 8, 1998
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Yasushi Takahashi, Hidetoshi Iwai, Satoshi Oguchi, Hisashi Nakamura, Hiroyuki Uchiyama, Toshitugu Takekuma, Shigetoshi Sakomura, Kazuyuki Miyazawa, Masamichi Ishihara, Ryoichi Hori, Takeshi Kizaki, Yoshihisa Koyama, Haruo Ii, Masaya Muranaka, Hidetomo Aoyagi, Hiromi Matsuura
  • Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor
    Patent number: 5426613
    Abstract: A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
    Type: Grant
    Filed: November 6, 1992
    Date of Patent: June 20, 1995
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Yasushi Takahashi, Hidetoshi Iwai, Satoshi Oguchi, Hisashi Nakamura, Hiroyuki Uchiyama, Toshitugu Takekuma, Shigetoshi Sakomura, Kazuyuki Miyazawa, Masamichi Ishihara, Ryoichi Hori, Takeshi Kizaki, Yoshihisa Koyama, Haruo Ii, Masaya Muranaka, Hidetomo Aoyagi, Hiromi Matsuura
  • Special mode control method for dynamic random access memory
    Patent number: 5410507
    Abstract: A dynamic RAM provided with a data retention mode intended for low power consumption is provided. In the data retention mode, the current supply capabilities of voltage generation circuits which generate decreased voltage, increased voltage, reference voltage, etc., are limited in the range in which information retention operation in memory cells can be maintained, and the number of selected memory mats in the data retention mode is increased with respect to that of memory mats selected in the normal read/write mode and refresh mode. Special modes such as the data retention mode are set by combining an address strobe signal and other control signals and dummy CBR refresh is executed to release the special mode.
    Type: Grant
    Filed: November 16, 1992
    Date of Patent: April 25, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Tazunoki, Shigetoshi Sakomura, Toshitsugu Takekuma, Yutaka Ito, Kazuya Ito, Wataru Arakawa, Hidetoshi Iwai, Toshiyuki Sakuta, Masamichi Ishihara
  • Semiconductor memory device
    Patent number: 5359561
    Abstract: A semiconductor memory device is provided which includes a plurality of data lines, at least one redundant data line, one common data line, a plurality of column switches installed between the plurality of data lines and the redundant data line and one common data line, and a column decoder for controlling the plurality of column switches. The column decoder operates to turn the column switch on. The column switch is connected to a plurality of data lines, excluding any defective data and redundant data lines during the test mode state.
    Type: Grant
    Filed: April 23, 1992
    Date of Patent: October 25, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Shigetoshi Sakomura, Kazuya Ito, Hidetoshi Iwai, Toshiyuki Sakuta, Masamichi Ishihara, Tomoshi Matsumoto, deceased
  • Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor
    Patent number: 5217917
    Abstract: A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
    Type: Grant
    Filed: March 20, 1990
    Date of Patent: June 8, 1993
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Yasushi Takahashi, Hidetoshi Iwai, Satoshi Oguchi, Hisashi Nakamura, Hiroyuki Uchiyama, Toshitugu Takemuma, Shigetoshi Sakomura, Kazuyuki Miyazawa, Masamichi Ishihara, Ryoichi Hori, Takeshi Kizaki, Yoshihisa Koyama, Haruo Ii, Masaya Muranaka, Hidetomo Aoyagi, Hiromi Matsuura