Patents by Inventor Shih-Chi Hsu

Shih-Chi Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Patent number: 11984419
    Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
  • Publication number: 20240136463
    Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 25, 2024
    Applicant: EPISTAR CORPORATION
    Inventors: Yi-Chieh LIN, Shiuan-Leh LIN, Yung-Fu CHANG, Shih-Chang LEE, Chia-Liang HSU, Yi HSIAO, Wen-Luh LIAO, Hong-Chi SHIH, Mei-Chun LIU
  • Patent number: 11916126
    Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: February 27, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Hsin Hsu, Huan-Chi Ma, Chien-Wen Yu, Shih-Min Chou, Nien-Ting Ho, Ti-Bin Chen
  • Patent number: 7841853
    Abstract: This invention discloses an injection molding machine and a heat-insulating structure of a barrel thereof. The heat-insulating structure covers the barrel of the injection molding machine. The heat-insulating structure includes a plurality of heat-insulating units and a plurality of heat-resistant interlinings. The heat-insulating units are disposed on an outer surface of the barrel in turn along an axial direction of the barrel. The heat-resistant interlinings are located between the heat-insulating units and connect the heat-insulating units, respectively. Each heat-insulating unit includes a heat-resistant layer, a heat-insulating material layer, and an insulating layer in turn. The heat-resistant layer covers the outer surface of the barrel of the injection molding machine.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: November 30, 2010
    Assignees: Maintek Computer (Suzhou) Co., Ltd., Pegatron Corporation
    Inventors: Chiu-ting Yu, Hsien-chih Wu, Yu-xiu Wu, Bo-tao Jiang, Shih-chi Hsu
  • Publication number: 20100028482
    Abstract: This invention discloses an injection molding machine and a heat-insulating structure of a barrel thereof. The heat-insulating structure covers the barrel of the injection molding machine. The heat-insulating structure includes a plurality of heat-insulating units and a plurality of heat-resistant interlinings. The heat-insulating units are disposed on an outer surface of the barrel in turn along an axial direction of the barrel. The heat-resistant interlinings are located between the heat-insulating units and connect the heat-insulating units, respectively. Each heat-insulating unit includes a heat-resistant layer, a heat-insulating material layer, and an insulating layer in turn. The heat-resistant layer covers the outer surface of the barrel of the injection molding machine.
    Type: Application
    Filed: July 30, 2009
    Publication date: February 4, 2010
    Applicants: Maintek Computer (Suzhou)Co. Ltd., Pegatron Corporation
    Inventors: Chiu-ting Yu, Hsien-chih Wu, Yu-xiu Wu, Bo-tao Jiang, Shih-chi Hsu
  • Patent number: 6221786
    Abstract: This present invention provides methods for isolating interconnects characterized by first isolating the top and bottom interconnects with an IMD consisting of a traditional low-k dielectric material, then dissolving the low-k material with a suitable solvent and using air or a noble gas instead of the traditional low-k dielectric material to isolate the interconnects.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: April 24, 2001
    Assignee: Nanya Technology Corporation
    Inventors: Shih-Chi Hsu, Tse Yao Huang
  • Patent number: 6140179
    Abstract: The present invention discloses a method of forming a crown capacitor for a DRAM cell. An etching method having different selectivity between the BPSG and silicon oxynitride layer is applied to form a sacrificial structure with a concanovenex sidewall. Using the sacrificial structure as a mold, a high capacitance crown capacitor is obtained.
    Type: Grant
    Filed: June 7, 1999
    Date of Patent: October 31, 2000
    Assignee: Nanya Technology Corporation
    Inventors: Yinan Chen, Shih-chi Hsu, Tse Yao Huang
  • Patent number: 6133089
    Abstract: A method for fabricating a DRAM capacitor is described. First, a semiconductor substrate having a capacitor contact is provided. Next, a first polysilicon layer is formed. Then, an oxide layer and a silicon oxy-nitride layer are sequentially formed over the first polysilicon layer. Next, the silicon oxy-nitride layer, the oxide layer, and the first polysilicon layer are selectively etched to leave a rectangular stack layer. Afterwards, the oxide layer and the first polysilicon layer of the rectangular stack layer are etched from the sidewall direction to leave a double T-shaped stack layer. Then, second polysilicon layer is formed on the upper surface and the sidewall of the double T-shaped stack layer. Next, the second polysilicon layer is selectively removed. The remaining second and first polysilicon layer are used as the bottom electrode. Afterwards, a dielectric layer and an upper electrode are formed on the bottom electrode.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: October 17, 2000
    Assignee: Nanya Technology Corporation
    Inventors: Tse Yao Huang, Shih-Chi Hsu, Yinan Chen, Hsing-Chuan Tsai