Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a base structure. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching the channel structures. The semiconductor device structure further includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. In addition, the semiconductor device structure includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.

Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A memory device includes a power supply device, a power-on-reset device, a memory array, and a memory controller. The power supply device converts the external supply voltage into an internal supply voltage. When the external supply voltage exceeds a first threshold, the power-on-reset device generates a reset signal. The power-on-reset device further raises the first threshold to a second threshold according to a deep-sleep signal. The memory array is supplied with the internal supply voltage. The memory controller is supplied with the internal supply voltage, accesses the memory array, and is reset according to the reset signal. When the memory controller operates in a deep-sleep mode, the memory controller generates the deep-sleep mode.

Abstract: A memory device includes a power supply device, a power-on-reset device, a memory array, and a memory controller. The power supply device converts the external supply voltage into an internal supply voltage. When the external supply voltage exceeds a first threshold, the power-on-reset device generates a reset signal. The power-on-reset device further raises the first threshold to a second threshold according to a deep-sleep signal. The memory array is supplied with the internal supply voltage. The memory controller is supplied with the internal supply voltage, accesses the memory array, and is reset according to the reset signal. When the memory controller operates in a deep-sleep mode, the memory controller generates the deep-sleep mode.

Abstract: An extending device includes a first riser card, a signal coupling card and a second riser card. A first electric socket of the first riser card is disposed on a side surface of a first circuit board of the first riser card, and a first electric connector is disposed at an edge of the first circuit board. A second electric connector and a third electric connector of the signal coupling card are respectively disposed on both side surfaces of a third circuit board of the signal coupling card. The second electric connector inserts into the first electric socket. A second electric socket and an extending socket of the second riser are respectively disposed on both side surfaces of a second circuit board of the second riser. The third electric connector inserts into the second electric socket and the extending socket is electrically connected to the second electric socket.

Abstract: An extending device includes a first riser card, a signal coupling card and a second riser card. A first electric socket of the first riser card is disposed on a side surface of a first circuit board of the first riser card, and a first electric connector is disposed at an edge of the first circuit board. A second electric connector and a third electric connector of the signal coupling card are respectively disposed on both side surfaces of a third circuit board of the signal coupling card. The second electric connector inserts into the first electric socket. A second electric socket and an extending socket of the second riser are respectively disposed on both side surfaces of a second circuit board of the second riser. The third electric connector inserts into the second electric socket and the extending socket is electrically connected to the second electric socket.

Abstract: A chip package structure including a carrier, a chip and a molding compound is provided. The chip is disposed on the carrier. The molding compound encapsulates a portion of the carrier and the chip. The top surface of the molding compound has a pin one dot and a pin gate contact. The pin one dot is located at a first corner on the top surface. The pin gate contact is located at a second corner except the first corner. The invention further provides a chip package mold chase and a chip package process using to form the chip package structure.

Abstract: A chip package structure including a carrier, a chip and a molding compound is provided. The chip is disposed on the carrier. The molding compound encapsulates a portion of the carrier and the chip. The top surface of the molding compound has a pin one dot and a pin gate contact. The pin one dot is located at a first corner on the top surface. The pin gate contact is located at a second corner except the first corner. The invention further provides a chip package mold chase and a chip package process using to form the chip package structure.

Abstract: A socket includes faces, grooves and groups of notches. Each of the grooves is located between two adjacent one of the faces. Each of the grooves includes a width that gets smaller towards an axis of the socket along a radius, thus defining a reduced neck. Each of the groups of notches is located along a related one of the grooves or in a related one of the faces.