Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A heat dissipation system and a coolant distribution module for plural electronic components of an electronic computing device are provided. The heat dissipation system includes plural water-cooling heads, a heat dissipation device and the coolant distribution module. When a fluid medium flows through the heat dissipation device, the heat dissipation device exchanges heat with the fluid medium. The coolant distribution module is connected between the plural water-cooling heads and the heat dissipation device. The coolant distribution module includes a main body and a power module. The module main body includes a cooled fluid chamber. The cooled fluid chamber includes plural first outlets corresponding to the plural water-cooling heads. The power module is installed in the module main body. The power module drives the fluid medium to be outputted from the plural first outlets. Consequently, the fluid medium is transferred through a circulating loop.

Abstract: A signal plug including an external sleeve, a line-connecting portion and a plug main-part. The line-connecting portion has two metallic end pieces separated by an insulation member, and a front end extending to form an insertion-connecting portion. The main-part includes the line-connecting portion inserted into a front end of an outer hard metallic receiving portion. The external sleeve is connected to the main-part with the insertion-connecting portion extending outwardly from the external sleeve. The outer receiving portion is made of phosphor bronze and will not deform during assembling. The inner line-connecting portion is made of high electric conductivity copper.

Abstract: A cleaning method used in the fabrication of metallic interconnects is provided. A substrate having a conductive layer and a dielectric layer on the conductive layer is provided. An opening is formed in the dielectric layer. The opening exposes a portion of the conductive layer. The opening is cleaned using a mixture containing sulfuric acid and hydrogen peroxide. In this invention, the mixture containing sulfuric acid and hydrogen peroxide provides an effective means of removing the residues within the opening so that the electrical conductivity of a subsequently formed contact is improved.

Abstract: A method of metal etching post cleaning. A substrate with a surface covered by a patterned metal layer and a patterned resist layer in order is provided, subsequently, oxygen-plasma ashing is performed to remove the patterned resist layer to expose the surface of the patterned metal layer. Next, an ozone-plasma ashing is performed to release charges on the surface of the patterned metal layer, the ozone-plasma ashing time at 30 sec˜180 sec, and the ozone-plasma ashing temperature at 200° C.˜300° C. The surface of the patterned metal layer is finally cleaned with sulfuric peroxide, molar concentration of sulfuric acid and hydrogen peroxide therein being 0.07M˜0.4M and 0.8M˜1.5M, respectively. In addition, the temperature of the sulfuric peroxide during post cleaning is 25° C.˜50° C.

Abstract: A structure of a speaker signal line having a middle filler layer, a plurality of transmission conductors and an outer coating portion, wherein, the middle filler layer is comprised of many hollow tubes. The transmission conductors are equidistantly spaced and wrapped over the middle filler layer. The coating portion is made of polyvinyl chloride composition. The middle filler lay is formed in the way of entangling to increase its strength and flexibility. The transmission conductors are spaced mutually in different layers and wrapped over the middle filler layer in mutual contrary directions. All the elements above are combined together by adding the outer coating portion, thereby, the inductive resistance induced by the transmission conductors equidistantly spaced in different layers and wrapped in mutual contrary directions can be mutually offset.

Abstract: A structure of signal line comprising a core portion, a middle filler layer, an obscuring layer and a coating portion, the core portion is a transmission conductor with a rectangular cross section; the obscuring layer has at least a knitted metallic obscuring layer; the coating portion has at least a layer made of polyvinyl chloride composition; and the middle filler layer is comprised of a plurality of hollow tubes. The core portion is tangled with the middle filler layer to make the line stronger in addition to being flexible, so that the line will not have the core portion damaged when it is bent to deform, plus the obscuring function of the obscuring layer, the interference among a magnetic field, radio frequencies and static electricity can be reduced, thereby, attenuation rate of the line can be reduced, distortion of the line can be smaller, and high quality of the line can be obtained.

Abstract: A structure of signal line comprising a core portion, a middle filler layer, an obscuring layer and a coating portion, the core portion is a transmission conductor with a rectangular cross section; the obscuring layer has at least a knitted metallic obscuring layer; the coating portion has at least a layer made of polyvinyl chloride composition; and the middle filler layer is comprised of a plurality of hollow tubes. The core portion is tangled with the middle filler layer to make the line stronger in addition to being flexible, so that the line will not have the core portion damaged when it is bent to deform, plus the obscuring function of the obscuring layer, the interference among a magnetic field, radio frequencies and static electricity can be reduced, thereby, attenuation rate of the line can be reduced, distortion of the line can be smaller, and high quality of the line can be obtained.

Abstract: A structure of a speaker signal line, comprising a middle filler layer, a plurality of transmission conductors and an outer coating portion, wherein, the middle filler layer is comprised of many hollow tubes; the transmission conductors are equidistantly spaced and wrapped over the middle filler layer; the coating portion is made of polyvinyl chloride composition; and wherein, the middle filler layer is formed in the way of entangling to increase its strength and flexibility. The transmission conductors are spaced mutually in different layers and wrapped over the middle filler layer in mutual contrary directions; all the elements above are combined together by adding the outer coating portion, thereby, the inductive resistance induced by the transmission conductors equidistantly spaced in different layers and wrapped in mutual contrary directions can be mutually offset, this lowers mutual interference and has the transmission speed and transmission quality of the signal line increased.

Abstract: A method of metal etching post cleaning. A substrate with a surface covered by a patterned metal layer and a patterned resist layer in order is provided, subsequently, oxygen-plasma ashing is performed to remove the patterned resist layer to expose the surface of the patterned metal layer. Next, an ozone-plasma ashing is performed to release charges on the surface of the patterned metal layer, the ozone-plasma ashing time at 30 sec˜180 sec, and the ozone-plasma ashing temperature at 200° C.˜300° C. The surface of the patterned metal layer is finally cleaned with sulfuric peroxide, molar concentration of sulfuric acid and hydrogen peroxide therein being 0.07M˜0.4M and 0.8M˜1.5M, respectively. In addition, the temperature of the sulfuric peroxide during post cleaning is 25° C.˜50° C.

Abstract: A gate dielectric breakdown test method is disclosed. The method includes performing a one step programmed VRDB test using Vcc voltage power source, gate current density for the corresponding ramped voltages are recorded. If the gate current density is found to be higher than a specified gate current density criterion, then the gate oxide is deemed to defective and is scrapped. And, if the gate current density (Jg) is found to be less than the specified gate current density criterion (Jc), then a differential gate current density ratio R=&Dgr;Jg/Jg for the corresponding ramped voltages are calculated. If the R value is found to be less than a specified differential current density ratio criterion (Rc), then the gate dielectric is considered to be robust, and if the R value is greater than the Rc value, then the gate dielectric is considered to be inflected. Accordingly, the voltage Vg can be effectively used for justifying the integrity of the gate dielectric.

Abstract: A via plug layout structure for connecting different metallic layers. The structure includes a plurality of via plugs arranged in a fan-shaped pattern and a plurality of empty bars positioned between a single via plug and the fanned-out via plugs so that incoming current to the single via plug is equally distributed to every one of the fanned-out via plug and current stress in each fanned-out via plug is identical. Hence, via plugs having particularly serious electromigration problem can be discovered. In addition, single via plug having different critical dimension can be fabricated so that maximum critical dimension sustainable by the via plug is determined after an electromigration test.

Abstract: A gate dielectric breakdown test method is disclosed. The method includes performing a one step programmed VRDB test using Vcc voltage power source, gate current for the corresponding ramped voltages are recorded. If the gate current density is found to be higher than a specified gate current criterion, then the gate oxide is deemed to defective and is scrapped. And, if the gate current density (Jg) is found to be less than the specified gate current criterion (Jc), then a differential gate current density ratio R=Jg/Jg for the corresponding ramped voltages are calculated. If the R value is found to be less than a specified differential current density ratio criterion (Rc), then the gate dielectric is considered to be robust, and if the R value is greater than the Rc value, then the gate dielectric is considered to be inflected. Accordingly, the voltage Vg can be effectively used for justifying the integrity of the gate dielectric.

Abstract: The present invention provides a method for preventing gate oxides on a semiconductor wafer from being damaged by electromagnetic waves or particles generated in a plasma-related process. The semiconductor wafer comprises a substrate, a plurality of gate oxides positioned separately on the substrate, a first dielectric layer positioned on the gate oxides for isolating the gate oxides, and a conducting layer positioned on the first dielectric layer having at least one testing slit with a predetermined test pattern installed above each of the gate oxides. The method first performs a predetermined plasma-related process on the surface of the semiconductor wafer. Next, an electrical test is performed to find damaged gate oxides out of the gate oxides on the substrate. Based on damages of the damaged gate oxides, the predetermined plasma-related process is adjusted to prevent gate oxides on other semiconductor wafers from being damaged in the predetermined plasma-related process.