Patents by Inventor Shih-Chin Lin
Shih-Chin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9437577Abstract: A package on package (POP) structure includes at least a first package and a second package. The first package has a plurality of pillar bump pins. The second package has a plurality of pads connected to the pillar bump pins, respectively. A method of forming a package on package (POP) structure includes at least the following steps: providing a first package with a plurality of pillar bump pins; providing a second package with a plurality of pads; and forming the POP structure by connecting the pillar bump pins to the pads.Type: GrantFiled: May 9, 2014Date of Patent: September 6, 2016Assignee: MEDIATEK INC.Inventors: Wen-Sung Hsu, Shih-Chin Lin
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Publication number: 20160208403Abstract: A brushless rotary plasma electrode structure is disclosed. The brushless rotary plasma electrode structure includes a main body, a plurality of guided portions, and a plurality of conducting-through members. The main body further includes a plurality of electrode portions that have a first salient portion furnished at the periphery thereof. The guided portion is penetrated through the electrode portion. Each of the conducting-through members further includes a second salient portion. There is an internal in both the first salient portion and the second salient portion. In addition, a film coating system is also provided.Type: ApplicationFiled: September 1, 2015Publication date: July 21, 2016Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Shih-Chin LIN, Chia-Hao CHANG, Kuang-Yu LIN
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Publication number: 20160180539Abstract: A graphic processing circuit with binning rendering and associated pre-depth processing method is provided. Firstly, a first depth data of a first primitive corresponding to a specified tile is received. Then, the pre-depth data corresponding to the specified tile is read from a pre-Z buffer. If the first depth data is not larger than the pre-depth data and the first primitive is an opaque primitive, the pre-depth data is updated with the first depth data. If the first depth data is not larger than the pre-depth data and the first primitive is a translucent primitive, an uncertainty ordering range is defined according to the first depth data and the pre-depth data, and the pre-depth data is updated with the uncertainty ordering range.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: Ming-Hao Liao, Chih-Ching Chen, Shih-Chin Lin, Hung-Wei Wu
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Publication number: 20160172292Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate structure having a cavity. A bottom surface of the cavity serves as a die-attach surface of the substrate structure. A semiconductor die is disposed in the cavity and mounted on the die-attach surface. A sidewall of the cavity is separated from the semiconductor die. An interposer is disposed on the substrate structure, covering the cavity.Type: ApplicationFiled: October 23, 2015Publication date: June 16, 2016Inventors: Wen-Sung HSU, Shih-Chin LIN
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Publication number: 20160172334Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.Type: ApplicationFiled: June 11, 2015Publication date: June 16, 2016Inventors: Wen-Sung HSU, Shih-Chin LIN, Andrew C. CHANG, Tao CHENG
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Patent number: 9361697Abstract: A graphic processing circuit with binning rendering and associated pre-depth processing method is provided. Firstly, a first depth data of a first primitive corresponding to a specified tile is received. Then, the pre-depth data corresponding to the specified tile is read from a pre-Z buffer. If the first depth data is not larger than the pre-depth data and the first primitive is an opaque primitive, the pre-depth data is updated with the first depth data. If the first depth data is not larger than the pre-depth data and the first primitive is a translucent primitive, an uncertainty ordering range is defined according to the first depth data and the pre-depth data, and the pre-depth data is updated with the uncertainty ordering range.Type: GrantFiled: December 23, 2014Date of Patent: June 7, 2016Assignee: MEDIATEK INC.Inventors: Ming-Hao Liao, Chih-Ching Chen, Shih-Chin Lin, Hung-Wei Wu
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Patent number: 9252068Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; a non-planar shaped heat spreading layer, formed over the spacer; an encapsulant layer, formed, over the circuit board, filling spaces between the non-planar shaped heat spreading layer and the circuit board; and a plurality of solder balls, formed over the second surface of the circuit board.Type: GrantFiled: February 2, 2015Date of Patent: February 2, 2016Assignee: MEDIATEK INC.Inventors: Tai-Yu Chen, Chung-Fa Lee, Wen-Sung Hsu, Shih-Chin Lin
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Publication number: 20150325549Abstract: A package on package (POP) structure includes at least a first package and a second package. The first package has a plurality of pillar bump pins. The second package has a plurality of pads connected to the pillar bump pins, respectively. A method of forming a package on package (POP) structure includes at least the following steps: providing a first package with a plurality of pillar bump pins; providing a second package with a plurality of pads; and forming the POP structure by connecting the pillar bump pins to the pads.Type: ApplicationFiled: May 9, 2014Publication date: November 12, 2015Applicant: MEDIATEK INC.Inventors: Wen-Sung Hsu, Shih-Chin Lin
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Patent number: 9184107Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board, wherein a ratio between the first cross sectional dimension and the second cross sectional dimension is about 1:2-1:6.Type: GrantFiled: December 30, 2014Date of Patent: November 10, 2015Assignee: MEDIATEK INC.Inventors: Tai-Yu Chen, Chung-Fa Lee, Wen-Sung Hsu, Shih-Chin Lin
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Publication number: 20150147890Abstract: A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode.Type: ApplicationFiled: December 23, 2013Publication date: May 28, 2015Applicant: Industrial Technology Research InstituteInventors: Kung-Liang Lin, Chien-Chih Chen, Fu-Ching Tung, Chih-Yung Chen, Shih-Chin Lin, Kuan-Yu Lin, Chia-Hao Chang, Shieh-Sien Wu
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Publication number: 20150145113Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; a non-planar shaped heat spreading layer, formed over the spacer; an encapsulant layer, formed, over the circuit board, filling spaces between the non-planar shaped heat spreading layer and the circuit board; and a plurality of solder balls, formed over the second surface of the circuit board.Type: ApplicationFiled: February 2, 2015Publication date: May 28, 2015Inventors: Tai-Yu CHEN, Chung-Fa LEE, Wen-Sung HSU, Shih-Chin LIN
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Patent number: 9023693Abstract: A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode.Type: GrantFiled: December 23, 2013Date of Patent: May 5, 2015Assignee: Industrial Technology Research InstituteInventors: Kung-Liang Lin, Chien-Chih Chen, Fu-Ching Tung, Chih-Yung Chen, Shih-Chin Lin, Kuan-Yu Lin, Chia-Hao Chang, Shieh-Sien Wu
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Publication number: 20150115429Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board, wherein a ratio between the first cross sectional dimension and the second cross sectional dimension is about 1:2-1:6.Type: ApplicationFiled: December 30, 2014Publication date: April 30, 2015Inventors: Tai-Yu CHEN, Chung-Fa LEE, Wen-Sung HSU, Shih-Chin LIN
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Patent number: 9000581Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board.Type: GrantFiled: May 17, 2013Date of Patent: April 7, 2015Assignee: MediaTek Inc.Inventors: Tai-Yu Chen, Chung-Fa Lee, Wen-Sung Hsu, Shih-Chin Lin
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Patent number: 8927878Abstract: Embodiments of a printed circuit board (PCB) and an electronic apparatus are provided. The PCB includes a PCB substrate and a plurality of the pads. The PCB substrate is disposed with the plurality of the pads. The plurality of the pads include a first type of the pads and a second type of the pads. The first type of the pads adopts the solder mask defined structure, and the second type of the pads adopts the non-solder mask defined structure.Type: GrantFiled: October 30, 2012Date of Patent: January 6, 2015Assignee: MediaTek Singapore Pte. LtdInventors: Jieyun Jiang, Shih-Chin Lin, Fu-Kang Pan, Yang Liu, Hung-Chang Hung
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Patent number: 8896135Abstract: Disclosed is an encapsulation film. An inorganic oxide film is formed on an organic sealing layer by an atomic layer deposition (ALD) to form the encapsulation film, wherein the organic sealing layer is a polymer containing hydrophilic groups. The organic sealing layer and the inorganic oxide layer have covalent bondings therebetween. The encapsulation film can solve the moisture absorption problem of conventional organic sealing layers, thereby being suitable for use as a package of optoelectronic devices.Type: GrantFiled: January 4, 2011Date of Patent: November 25, 2014Assignee: Industrial Technology Research InstituteInventors: Ching-Chiun Wang, Kang-Feng Lee, Feng-Yu Tsai, Ming Horn Zheng, Chih-Yung Huang, Shih-Chin Lin, Jen-Rong Huang
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Publication number: 20140140120Abstract: A memory cell includes six transistors. The first and second P-type transistors have the sources coupled to a first voltage. The first and second N-type transistors have the drains coupled to drains of the first and second P-type transistors, respectively; the sources coupled to a second voltage; and the gates coupled to gates of the first and second P-type transistors, respectively. The third N-type transistor has the drain coupled to a write word line; the source coupled to drain of the first N-type transistor and gate of the second N-type transistor; and the gate coupled to a first write bit line. The fourth N-type transistor has the drain coupled to the write word line; the source coupled to drain of the second N-type transistor and gate of the first N-type transistor; and the gate coupled to a second write bit line. A memory cell array is also provided.Type: ApplicationFiled: November 21, 2012Publication date: May 22, 2014Applicant: United Microelectronics CorporationInventors: Hsin-Wen CHEN, Chi-Chang SHUAI, Shih-Chin LIN
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Patent number: 8711598Abstract: A memory cell includes six transistors. The first and second P-type transistors have the sources coupled to a first voltage. The first and second N-type transistors have the drains coupled to drains of the first and second P-type transistors, respectively; the sources coupled to a second voltage; and the gates coupled to gates of the first and second P-type transistors, respectively. The third N-type transistor has the drain coupled to a write word line; the source coupled to drain of the first N-type transistor and gate of the second N-type transistor; and the gate coupled to a first write bit line. The fourth N-type transistor has the drain coupled to the write word line; the source coupled to drain of the second N-type transistor and gate of the first N-type transistor; and the gate coupled to a second write bit line. A memory cell array is also provided.Type: GrantFiled: November 21, 2012Date of Patent: April 29, 2014Assignee: United Microelectronics Corp.Inventors: Hsin-Wen Chen, Chi-Chang Shuai, Shih-Chin Lin
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Publication number: 20130313698Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board.Type: ApplicationFiled: May 17, 2013Publication date: November 28, 2013Applicant: MediaTek Inc.Inventors: Tai-Yu CHEN, Chung-Fa LEE, Wen-Sung HSU, Shih-Chin LIN
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Patent number: 8576653Abstract: In an exemplary hidden refresh method for a pseudo SRAM, a system clock is received. A duty-on period of the system clock signal is adapted for performing a data access operation such as write or read operation. A refresh clock signal subjected to the control of the system clock signal is generated. A duty-on period of the refresh clock signal is non-overlapped with the duty-on period of the system clock signal. A refresh control pulse then is triggered by a starting edge of the duty-on period of the refresh clock signal to activate a word line, for performing a refresh operation.Type: GrantFiled: July 1, 2011Date of Patent: November 5, 2013Assignee: United Microelectronics Corp.Inventors: Shih-Chin Lin, Pei-Geng Ma, Yen-Hsueh Huang