Patents by Inventor Shih-Fan Chen
Shih-Fan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947153Abstract: A backlight module and a display device are provided, and the backlight module includes a light guide plate, a plurality of light-emitting components, and a frame. The light guide plate includes a first side, a second side, and two third sides. The light-emitting components are disposed on the first side, and light generated from the light-emitting components enters the light guide plate from the first side. The frame covers the second side and the third sides and includes an opening and at least one buffer portion. The light-emitting components are disposed in the opening, and the buffer portion is disposed on a side of the opening and contacts the light guide plate.Type: GrantFiled: May 4, 2023Date of Patent: April 2, 2024Assignee: Radiant Opto-Electronics CorporationInventors: Hung-Pin Cheng, Shih-Fan Liu, Chien-Yu Ko, Jui-Lin Chen
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Patent number: 11876089Abstract: A voltage clamp is disclosed. The voltage clamp may include a plurality of transistors to limit the voltage between a power supply and ground. In addition, the voltage clamp may include a positive feedback signal to reduce turn-on time of the plurality of transistors.Type: GrantFiled: February 12, 2021Date of Patent: January 16, 2024Assignee: Synaptics IncorporatedInventors: Shih-Fan Chen, Abhijat Goyal
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Patent number: 11272616Abstract: An example apparatus includes a first printed circuit board (PCB) having a power layer, a ground layer, and a slot. The slot includes a first power electrical contact that is electrically connected to the power layer and a first ground electrical contact that is connected to the ground layer. The slot extends orthogonally or obliquely through multiple layers of the first PCB. A second PCB includes a second power electrical contact, a second ground electrical contact, and capacitors electrically connected between the second power electrical contact and the second ground electrical contact. The second PCB is configured for insertion into the slot to form an electrical connection between the first power electrical contact and the second power electrical contact and between the first ground electrical contact and the second ground electrical contact.Type: GrantFiled: July 24, 2020Date of Patent: March 8, 2022Assignee: TERADYNE, INC.Inventors: Brian Brecht, Roger A. Plante, Richard Pye, Julie Robison, Alfred M. Zakarian, William Patti, Mark Garcia, Shih-Fan Chen, Kenneth L. Degan, Heng-Kit Too
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Publication number: 20220030718Abstract: An example apparatus includes a first printed circuit board (PCB) having a power layer, a ground layer, and a slot. The slot includes a first power electrical contact that is electrically connected to the power layer and a first ground electrical contact that is connected to the ground layer. The slot extends orthogonally or obliquely through multiple layers of the first PCB. A second PCB includes a second power electrical contact, a second ground electrical contact, and capacitors electrically connected between the second power electrical contact and the second ground electrical contact. The second PCB is configured for insertion into the slot to form an electrical connection between the first power electrical contact and the second power electrical contact and between the first ground electrical contact and the second ground electrical contact.Type: ApplicationFiled: July 24, 2020Publication date: January 27, 2022Inventors: Brian Brecht, Roger A. Plante, Richard Pye, Julie Robison, Alfred M. Zakarian, William Patti, Mark Garcia, Shih-Fan Chen, Kenneth L. Degan, Heng-Kit Too
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Publication number: 20210257353Abstract: A voltage clamp is disclosed. The voltage clamp may include a plurality of transistors to limit the voltage between a power supply and ground. In addition, the voltage clamp may include a positive feedback signal to reduce turn-on time of the plurality of transistors.Type: ApplicationFiled: February 12, 2021Publication date: August 19, 2021Inventors: Shih-Fan CHEN, Abhijat GOYAL
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Publication number: 20200066709Abstract: A semiconductor device includes a P-type substrate, a first isolation region, a plurality of first N-well walls, and an electrostatic discharge (ESD) clamp circuit. The first isolation region is formed within the P-type substrate. The ESD clamp circuit is arranged to discharge ESD current upon detection of an ESD event, and includes a clamping component that is arranged to provide a discharge path for the ESD current. The clamping component is formed on a region wrapped in the first isolation layer and the first N-well walls.Type: ApplicationFiled: August 2, 2019Publication date: February 27, 2020Inventors: Shih-Fan Chen, Kuo-Chun Hsu, Tai-Hsiang Lai
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Publication number: 20190172691Abstract: A heating carrier device for use on a sputtering cathode assembly has a heating carrier for heating a sputtering target to control a sputtering target temperature; a magnetic component for generating a magnetic field; a thermal insulation component disposed between the heating carrier and the magnetic component; and a cooling system for cooling the magnetic component. Therefore, the heating carrier device reduces the bonding strength of the sputtering target, reduces the particle size of sputtering products, and grows high-quality, uniform thin films.Type: ApplicationFiled: May 9, 2018Publication date: June 6, 2019Inventors: CHOU-YU LIN, HUI-YUN BOR, CHAO-NAN WEI, CHIEN-HUNG LIAO, SHEA-JUE WANG, SHIH-FAN CHEN
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Patent number: 9735144Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor layer having a first doped region, a second doped region, and an intrinsic region formed therein, and a plurality of insulating elements respectively formed therein. The plurality of insulating elements is respectively formed in a portion of the semiconductor layer between the first, second and third doped regions. The intrinsic region is formed at least in the semiconductor layer between one of the second and third regions and the other one of the second and third regions or between one of the second and third regions and the first region. The first doped region is formed with a first conductivity type, and the second and third doped regions are formed with a second conductivity type opposite to the first conductivity type.Type: GrantFiled: February 3, 2016Date of Patent: August 15, 2017Assignee: MEDIATEK INC.Inventors: Shih-Fan Chen, Tai-Hsiang Lai
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Publication number: 20160240524Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor layer having a first doped region, a second doped region, and an intrinsic region formed therein, and a plurality of insulating elements respectively formed therein. The plurality of insulating elements is respectively formed in a portion of the semiconductor layer between the first, second and third doped regions. The intrinsic region is formed at least in the semiconductor layer between one of the second and third regions and the other one of the second and third regions or between one of the second and third regions and the first region. The first doped region is formed with a first conductivity type, and the second and third doped regions are formed with a second conductivity type opposite to the first conductivity type.Type: ApplicationFiled: February 3, 2016Publication date: August 18, 2016Inventors: Shih-Fan CHEN, Tai-Hsiang LAI
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Patent number: 9001478Abstract: A self-reset transient-to-digital convertor which includes at least one transient detection circuit is disclosed. The transient detection circuit, coupled between a first power line and a second power line, includes at least one voltage drop unit, a current amplifier unit, and a time control unit. When an ESD event occurs, the voltage drop unit is conducted to pass through an ESD current. The current amplifier unit, coupled between the voltage drop unit and the first power line, is conducted by the ESD current to set the level of a first node. The time control unit, coupled between the first node and the second power line, is configured to gradually drain the ESD current away. Wherein, each of the transient detection circuit generates a digital code according to the level of the first node.Type: GrantFiled: December 16, 2011Date of Patent: April 7, 2015Assignees: National Chiao-Tung University, Himax Technologies LimitedInventors: Ming-Dou Ker, Cheng-Cheng Yen, Tung-Yang Chen, Ching-Ling Tsai, Shih-Fan Chen
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Publication number: 20130155566Abstract: A self-reset transient-to-digital convertor which includes at least one transient detection circuit is disclosed. The transient detection circuit, coupled between a first power line and a second power line, includes at least one voltage drop unit, a current amplifier unit, and a time control unit. When an ESD event occurs, the voltage drop unit is conducted to pass through an ESD current. The current amplifier unit, coupled between the voltage drop unit and the first power line, is conducted by the ESD current to set the level of a first node. The time control unit, coupled between the first node and the second power line, is configured to gradually drain the ESD current away. Wherein, each of the transient detection circuit generates a digital code according to the level of the first node.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicants: HIMAX TECHNOLOGIES LIMITED, NATIONAL CHIAO-TUNG UNIVERSITYInventors: MING-DOU KER, Cheng-Cheng Yen, Tung-Yang CHEN, Ching-Ling Tsai, Shih-Fan Chen
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Patent number: 8397201Abstract: A method of simulating an electrostatic discharge (ESD) circuit layout is disclosed. A netlist of an electronic circuit is pre-simulated. A circuit layout, including an ESD circuit layout, is accordingly generated. Parasitic is extracted according to the generated circuit layout. The ESD circuit layout is post-simulated according to an ESD waveform and a result of the parasitic extraction.Type: GrantFiled: August 11, 2011Date of Patent: March 12, 2013Assignee: Himax Technologies LimitedInventors: Ching-Ling Tsai, Shih-Fan Chen
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Publication number: 20130050884Abstract: An ESD protection circuit connected between an I/O pad and an internal circuit is disclosed. The ESD protection circuit includes a P type ESD protection element which has a first P type doped region, a first isolation structure and a first N type doped region. The first isolation structure is disposed inside the first P type doped region, and the first N type doped region is disposed to encompass said first P type doped region. During an ESD event, the first P type doped region of the P type ESD protection element receives an ESD current and drains it away, and the parasitical capacitance of the P type ESD protection element decreases based on the area of the first P type doped region.Type: ApplicationFiled: August 23, 2011Publication date: February 28, 2013Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Ching-Ling Tsai, Sheng-Fan Yang, Shih-Fan Chen
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Publication number: 20130044396Abstract: An ESD protection circuit connected between an I/O pad and an internal circuit is disclosed. The ESD protection circuit includes a P type ESD protection element which has a first P type doped region and a first N type doped region. The covered shape of the first P type doped region is circular, and the first N type doped region is disposed to encompass said first P type doped region. During an ESD event, the first P type doped region of the P type ESD protection element receives an ESD current and uniformly drains it away.Type: ApplicationFiled: August 17, 2011Publication date: February 21, 2013Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Ching-Ling Tsai, Shih-Fan Chen, Yu-Wei Huang
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Publication number: 20130042218Abstract: A method of simulating an electrostatic discharge (ESD) circuit layout is disclosed. A netlist of an electronic circuit is pre-simulated. A circuit layout, including an ESD circuit layout, is accordingly generated. Parasitic is extracted according to the generated circuit layout. The ESD circuit layout is post-simulated according to an ESD waveform and a result of the parasitic extraction.Type: ApplicationFiled: August 11, 2011Publication date: February 14, 2013Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Ching-Ling Tsai, Shih-Fan Chen