Abstract: An image processing apparatus and a processing method thereof are provided. The image processing apparatus includes an image capturing module, an image separation module, an image stabilization module, a temporal noise reduction module, and a spatial noise reduction module. The image capturing module captures a plurality of Bayer pattern images. The image separation module decreases the Bayer pattern images in size and transforms them into a plurality of YCbCr format images. The image stabilization module receives Y channel images of the YCbCr format images and the Bayer pattern images to perform motion estimation, to produce a plurality of global motion vectors (GMVs). The temporal noise reduction module performs temporal blending process on the Bayer pattern images according to the GMVs, to produce first noise reduction images. The spatial noise reduction module performs 2-dimensional spatial noise reduction on the first noise reduction images to produce second noise reduction images.

Abstract: An image processing apparatus and a processing method thereof are provided. The image processing apparatus includes an image capturing module, an image separation module, an image stabilization module, a temporal noise reduction module, and a spatial noise reduction module. The image capturing module captures a plurality of Bayer pattern images. The image separation module decreases the Bayer pattern images in size and transforms them into a plurality of YCbCr format images. The image stabilization module receives Y channel images of the YCbCr format images and the Bayer pattern images to perform motion estimation, to produce a plurality of global motion vectors (GMVs). The temporal noise reduction module performs temporal blending process on the Bayer pattern images according to the GMVs, to produce first noise reduction images. The spatial noise reduction module performs 2-dimensional spatial noise reduction on the first noise reduction images to produce second noise reduction images.

Abstract: A method for predicting the quantity of pictures that can be taken is applied to a picture-taking function of a digital still camera. Firstly, a lookup table is individually built for different power using operations of a battery according to the operational modes of the picture-taking function. Next, the method looks up the corresponding lookup table according to an obtained battery voltage value of the digital still camera and the operational mode. Finally, a quantity of pictures that can be taken is obtained from the lookup table, and is displayed on a display unit of the digital still camera and is provided to the user. Thereby, the user can change the operational mode to reduce power consumption and take more pictures.

Abstract: Methods for assembling thermally enhanced semiconductor device packages are disclosed in which a chip assembly has a chip affixed to a leadframe. A thermal pad is affixed to a surface of the chip, and the chip assembly is encapsulated whereby a surface of the thermal pad remains exposed to form at least a portion of a surface of the package favorable for the egress of heat from the chip. Also disclosed are thermally enhanced semiconductor device packages made using the methods of the invention.

Abstract: A method for predicting the quantity of pictures that can be taken is applied to a picture-taking function of a digital still camera. Firstly, a lookup table is individually built for different power using operations of a battery according to the operational modes of the picture-taking function. Next, the method looks up the corresponding lookup table according to an obtained battery voltage value of the digital still camera and the operational mode. Finally, a quantity of pictures that can be taken is obtained from the lookup table, and is displayed on a display unit of the digital still camera and is provided to the user. Thereby, the user can change the operational mode to reduce power consumption and take more pictures.

Abstract: A method for dynamically adjusting video frame is adapted to store video data to a cache memory with a plurality of registers. The method comprises the steps: first, receiving the video data and compressing the video frames; next, obtaining a first usage level of the cache memory; next, gathering statistics regarding the amount of registers that have been set at an indicating status in the circular queue; next, calculating a second usage level of the cache memory according to the amount of the indicating status; next, adjusting the size of the video frames by comparing the difference between the second usage level and the first usage level; and finally, storing the video data to the cache memory according to the size of the video frames. Thereby, all of the space of the cache memory is used fully to extend video recording time.

Abstract: A multi-layer structure unit of recording AV frame data includes a general control layer, a task control layer and a movie-format control layer. The general control layer is used to control a compression process of AV frame data, and manage a circular queue. The task control layer includes a plurality of control units, and is used to execute the necessary task of recording AV frame data with accessing the circular queue. Finally, the movie-format control layer is used for building a file with AV frame data. Hence, the multi-layer structure unit of recording AV frame data can improve the extensibility, the maintenance and the readability of software program.

Abstract: The present invention provides a picture transfer protocol (PTP) interface of an open architecture, which can be used on an operation interface of a digital device to enable vendors to develop vendor-defined commands by themselves. The open architecture of the picture transfer protocol includes a command interpreter which is used to execute standard commands and/or the vendor-defined commands, a command manager which is used to add or remove the standard commands and/or the vendor-defined commands, and a command set classification which is used to classify the standard commands and/or the vendor-defined commands.

Abstract: A system comprising a ball grid array (“BGA”) substrate adapted to electrically couple to an application board using a plurality of solder balls, and a film adapted to abut the application board and the BGA substrate, the film comprising a plurality of perforations, the solder balls adapted to couple to the application board through the perforations.

Abstract: A packaged integrated circuit that includes a substrate 310; a chip 300 mounted on the substrate; and a heatsink 350 mounted on the chip. The heatsink has a spacer 360 attached to one of its surfaces to provide a standoff distance between the heatsink and the substrate. The substrate and the heatsink can include moats into which the spacer is adapted to fit. The moat can be a notch at the edge of the substrate or it can be a channel or depression in the substrate surface. The spacer can be made of a high-modulus or low-modulus material, or a combination of the two.

Abstract: A method for forming solder bumps on a flip-chip semiconductor die using a wirebonder apparatus and a flip-chip die bumped according to the method disclosed. An embodiment of the invention includes feeding a solder wire through a wirebonder capillary, where the solder wire forms a solder sphere upon exiting the wirebonder capillary. The solder sphere may then be attached to a solder pad on a flip-chip die, compressing the solder sphere into a solder stud bond. The solder stud bond may then be severed from the solder wire and reflowed into a more spherical solder bump in an oven-reflow process.

Abstract: A low-CTE packaging material for assembling a semiconductor die into a package and a method for assembling a semiconductor die into a package, in which the packaging material comprises a negative-CTE material. The low-CTE packaging material in accordance with the embodiments of the invention may be a die attach material, a lid attach material, or an encapsulant, such as a mold compound or glob-top material. Preferably, the negative-CTE material is a tungstate compound, such as zirconium tungstate, halfnium tungstate or a solution of zirconium and halfnium tungstate.

Abstract: A packaged integrated circuit that includes a substrate 310; a chip 300 mounted on the substrate; and a heatsink 350 mounted on the chip. The heatsink has a spacer 360 attached to one of its surfaces to provide a standoff distance between the heatsink and the substrate. The substrate and the heatsink can include moats into which the spacer is adapted to fit. The moat can be a notch at the edge of the substrate or it can be a channel or depression in the substrate surface. The spacer can be made of a high-modulus or low-modulus material, or a combination of the two.