Patents by Inventor Shih-Hao Tseng
Shih-Hao Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948890Abstract: In an embodiment, a device includes: an integrated circuit die; a through via adjacent the integrated circuit die; a molding compound encapsulating the integrated circuit die and the through via; and a redistribution structure including: a first conductive via extending through a first dielectric layer, the first conductive via electrically connected to the integrated circuit die, the first dielectric layer being over the integrated circuit die, the through via, and the molding compound; and a first conductive line over the first dielectric layer and the first conductive via, the first conductive via extending into the first conductive line.Type: GrantFiled: June 7, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho
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Patent number: 11933809Abstract: The present application discloses an inertial sensor comprising a proof mass, an anchor, a flexible member and several sensing electrodes. The anchor is positioned on one side of the sensing, mass block in a first axis. The flexible member is connected to the anchor point and extends along the first axis towards the proof mass to connect the proof mass, in which the several sensing electrodes are provided. In this way, the present application can effectively solve the problems of high difficulty in the production and assembly of inertial sensors and poor product reliability thereof.Type: GrantFiled: April 6, 2022Date of Patent: March 19, 2024Assignee: SENSORTEK TECHNOLOGY CORP.Inventors: Shih-Wei Lee, Chia-Hao Lin, Shih-Hsiung Tseng, Kuan-Ju Tseng, Chao-Shiun Wang
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Publication number: 20230052776Abstract: A manufacturing method of a semiconductor package includes the following steps. An integrated circuit structure is provided, wherein the integrated circuit structure includes an integrated circuit and a metallization layer covering a back surface of the integrated circuit. An encapsulation material is provided to laterally encapsulate the integrated circuit structure. A redistribution structure is provided over the integrated circuit structure and the encapsulation material, wherein the redistribution structure includes a thermal metal layer furthermost from the integrated circuit structure, wherein the thermal metal layer is thermally coupled to the metallization layer. A solder layer is provided over the thermal metal layer, wherein the solder layer is thermally coupled to the thermal metal layer.Type: ApplicationFiled: November 2, 2022Publication date: February 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho
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Patent number: 11495507Abstract: A manufacturing method of a semiconductor package including the following steps is provided. A redistribution structure is formed over an encapsulated semiconductor device carried by a carrier, wherein the redistribution structure includes an organic polymer layer and a redistribution circuit layer electrically connected to the semiconductor device. An inorganic protection layer is formed to entirely cover an upper surface of the redistribution structure, wherein an oxygen and/or water vapor permeability of the inorganic protection layer is substantially lower than an oxygen and/or vapor permeability of the organic polymer layer. An adhesive is formed on the inorganic protection layer. An insulating cover is adhered on the inorganic protection layer through the adhesive.Type: GrantFiled: June 10, 2021Date of Patent: November 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho, Chia-Hung Liu
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Patent number: 11495506Abstract: A semiconductor package includes a first integrated circuit structure, a first encapsulation material laterally encapsulating the first integrated circuit structure, a first redistribution structure, a solder layer, a second integrated circuit structure, a second encapsulation material second laterally encapsulating the second integrated circuit structure and a second redistribution structure. The first integrated circuit structure includes a first metallization layer. The first redistribution structure is disposed over the first integrated circuit structure and first encapsulation material. The first metallization layer faces away from the first redistribution structure and thermally coupled to the first redistribution structure. The solder layer is dispose over the first redistribution structure. The second integrated circuit structure is disposed on the first redistribution structure and includes a second metallization layer in contact with the solder layer.Type: GrantFiled: March 30, 2020Date of Patent: November 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho
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Publication number: 20220352046Abstract: A semiconductor package includes a first integrated circuit, a first passivation layer, a second passivation layer, a thermal pattern, an adhesive layer and a second integrated circuit. The first integrated circuit is encapsulated by an encapsulant. The first passivation layer is disposed over the first integrated circuit and the encapsulant. The second passivation layer is disposed over the first passivation layer. The thermal pattern is disposed in the first passivation layer and the second passivation layer. The adhesive layer is disposed over the second passivation layer and in direct contact with the thermal pattern. The second integrated circuit is adhered to the first integrated circuit through the adhesive layer.Type: ApplicationFiled: April 28, 2021Publication date: November 3, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho
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Publication number: 20210305113Abstract: A manufacturing method of a semiconductor package including the following steps is provided. A redistribution structure is formed over an encapsulated semiconductor device carried by a carrier, wherein the redistribution structure includes an organic polymer layer and a redistribution circuit layer electrically connected to the semiconductor device. An inorganic protection layer is formed to entirely cover an upper surface of the redistribution structure, wherein an oxygen and/or water vapor permeability of the inorganic protection layer is substantially lower than an oxygen and/or vapor permeability of the organic polymer layer. An adhesive is formed on the inorganic protection layer. An insulating cover is adhered on the inorganic protection layer through the adhesive.Type: ApplicationFiled: June 10, 2021Publication date: September 30, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho, Chia-Hung Liu
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Publication number: 20210305112Abstract: A semiconductor package includes a first integrated circuit structure, a first encapsulation material laterally encapsulating the first integrated circuit structure, a first redistribution structure, a solder layer, a second integrated circuit structure, a second encapsulation material second laterally encapsulating the second integrated circuit structure and a second redistribution structure. The first integrated circuit structure includes a first metallization layer. The first redistribution structure is disposed over the first integrated circuit structure and first encapsulation material. The first metallization layer faces away from the first redistribution structure and thermally coupled to the first redistribution structure. The solder layer is dispose over the first redistribution structure. The second integrated circuit structure is disposed on the first redistribution structure and includes a second metallization layer in contact with the solder layer.Type: ApplicationFiled: March 30, 2020Publication date: September 30, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho
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Publication number: 20210296245Abstract: In an embodiment, a device includes: an integrated circuit die; a through via adjacent the integrated circuit die; a molding compound encapsulating the integrated circuit die and the through via; and a redistribution structure including: a first conductive via extending through a first dielectric layer, the first conductive via electrically connected to the integrated circuit die, the first dielectric layer being over the integrated circuit die, the through via, and the molding compound; and a first conductive line over the first dielectric layer and the first conductive via, the first conductive via extending into the first conductive line.Type: ApplicationFiled: June 7, 2021Publication date: September 23, 2021Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho
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Patent number: 11056412Abstract: A semiconductor package includes an encapsulated semiconductor device, a redistribution structure, and a protection layer. The encapsulated semiconductor device includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. The redistribution structure is disposed on the encapsulated semiconductor device and includes a dielectric layer and a redistribution circuit layer electrically connected to the semiconductor device. The protection layer at least covers the dielectric layer, wherein an oxygen permeability or a water vapor permeability of the protection layer is substantially lower than an oxygen permeability or a vapor permeability of the dielectric layer.Type: GrantFiled: July 22, 2019Date of Patent: July 6, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho, Chia-Hung Liu
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Patent number: 11031342Abstract: In an embodiment, a device includes: an integrated circuit die; a through via adjacent the integrated circuit die; a molding compound encapsulating the integrated circuit die and the through via; and a redistribution structure including: a first conductive via extending through a first dielectric layer, the first conductive via electrically connected to the integrated circuit die, the first dielectric layer being over the integrated circuit die, the through via, and the molding compound; and a first conductive line over the first dielectric layer and the first conductive via, the first conductive via extending into the first conductive line.Type: GrantFiled: March 19, 2018Date of Patent: June 8, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho
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Publication number: 20190341322Abstract: A semiconductor package includes an encapsulated semiconductor device, a redistribution structure, and a protection layer. The encapsulated semiconductor device includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. The redistribution structure is disposed on the encapsulated semiconductor device and includes a dielectric layer and a redistribution circuit layer electrically connected to the semiconductor device. The protection layer at least covers the dielectric layer, wherein an oxygen permeability or a water vapor permeability of the protection layer is substantially lower than an oxygen permeability or a vapor permeability of the dielectric layer.Type: ApplicationFiled: July 22, 2019Publication date: November 7, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho, Chia-Hung Liu
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Patent number: 10411990Abstract: Concepts and technologies disclosed herein are directed to routing stability in a hybrid software-defined networking (“SDN”) network in which control plane functionality is shared between a centralized SDN controller and a plurality of local routers. The controller can collect data plane messages from the plurality of local routers, extract information corresponding to source nodes and edges of a graph representative of the hybrid SDN network, and store the information as entries in a table. The controller can identify any outdated entries and remove any outdated entries from the table. The controller can obtain recovered information missing from the information collected from the data plane messages. The controller also can calculate an effective capacity of the edges. The controller can then generate a stable routing pattern based upon the recovered information and the effective capacity. The controller can deploy the stable routing pattern in the hybrid SDN network.Type: GrantFiled: December 18, 2017Date of Patent: September 10, 2019Assignees: AT&T Intellectual Property I, L.P., Cornell UniversityInventors: Shih-Hao Tseng, Ao Tang, Simon Tse, Gagan Choudhury
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Patent number: 10361139Abstract: A semiconductor package includes an encapsulated semiconductor device, a redistribution structure, and a protection layer. The encapsulated semiconductor device includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. The redistribution structure is disposed on the encapsulated semiconductor device and includes a dielectric layer and a redistribution circuit layer electrically connected to the semiconductor device. The protection layer at least covers the dielectric layer, wherein an oxygen permeability or a water vapor permeability of the protection layer is substantially lower than an oxygen permeability or a vapor permeability of the dielectric layer.Type: GrantFiled: January 31, 2018Date of Patent: July 23, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho, Chia-Hung Liu
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Publication number: 20190190814Abstract: Concepts and technologies disclosed herein are directed to routing stability in a hybrid software-defined networking (“SDN”) network in which control plane functionality is shared between a centralized SDN controller and a plurality of local routers. The controller can collect data plane messages from the plurality of local routers, extract information corresponding to source nodes and edges of a graph representative of the hybrid SDN network, and store the information as entries in a table. The controller can identify any outdated entries and remove any outdated entries from the table. The controller can obtain recovered information missing from the information collected from the data plane messages. The controller also can calculate an effective capacity of the edges. The controller can then generate a stable routing pattern based upon the recovered information and the effective capacity. The controller can deploy the stable routing pattern in the hybrid SDN network.Type: ApplicationFiled: December 18, 2017Publication date: June 20, 2019Applicants: AT&T Intellectual Property I, L.P., Cornell UniversityInventors: Shih-Hao Tseng, Ao Tang, Simon Tse, Gagan Choudhury
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Publication number: 20190148255Abstract: A semiconductor package includes an encapsulated semiconductor device, a redistribution structure, and a protection layer. The encapsulated semiconductor device includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. The redistribution structure is disposed on the encapsulated semiconductor device and includes a dielectric layer and a redistribution circuit layer electrically connected to the semiconductor device. The protection layer at least covers the dielectric layer, wherein an oxygen permeability or a water vapor permeability of the protection layer is substantially lower than an oxygen permeability or a vapor permeability of the dielectric layer.Type: ApplicationFiled: January 31, 2018Publication date: May 16, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho, Chia-Hung Liu
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Publication number: 20190148302Abstract: In an embodiment, a device includes: an integrated circuit die; a through via adjacent the integrated circuit die; a molding compound encapsulating the integrated circuit die and the through via; and a redistribution structure including: a first conductive via extending through a first dielectric layer, the first conductive via electrically connected to the integrated circuit die, the first dielectric layer being over the integrated circuit die, the through via, and the molding compound; and a first conductive line over the first dielectric layer and the first conductive via, the first conductive via extending into the first conductive line.Type: ApplicationFiled: March 19, 2018Publication date: May 16, 2019Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho
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Patent number: 9159304Abstract: A bore-variable leadpipe includes a mouthpiece receiver integrally formed on a tube body of a brass instrument and a mouthpiece adaptor detachably assembled to the mouthpiece receiver. The mouthpiece receiver internally defines a first bore, in which an assembling section, a tapered section and an air-guiding section are sequentially formed. The mouthpiece adaptor has a receiving end for receiving a mouthpiece therein and an assembling end for engaging with the assembling section, and internally defines a second bore between the two ends. When the mouthpiece adaptor is assembled to the mouthpiece receiver, the second and the first bore are aligned and communicable with each other to form a conical passage and a cylindrical passage. The leadpipe can be changed in its bore size by assembling a mouthpiece adaptor of a different bore size to the mouthpiece receiver, so that the same brass instrument can be used with differently sized mouthpieces.Type: GrantFiled: March 21, 2014Date of Patent: October 13, 2015Assignee: K.H.S. MUSICAL INSTRUMENT CO., LTD.Inventor: Shih Hao Tseng
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Publication number: 20150269919Abstract: A bore-variable leadpipe includes a mouthpiece receiver integrally formed on a tube body of a brass instrument and a mouthpiece adaptor detachably assembled to the mouthpiece receiver. The mouthpiece receiver internally defines a first bore, in which an assembling section, a tapered section and an air-guiding section are sequentially formed. The mouthpiece adaptor has a receiving end for receiving a mouthpiece therein and an assembling end for engaging with the assembling section, and internally defines a second bore between the two ends. When the mouthpiece adaptor is assembled to the mouthpiece receiver, the second and the first bore are aligned and communicable with each other to form a conical passage and a cylindrical passage. The leadpipe can be changed in its bore size by assembling a mouthpiece adaptor of a different bore size to the mouthpiece receiver, so that the same brass instrument can be used with differently sized mouthpieces.Type: ApplicationFiled: March 21, 2014Publication date: September 24, 2015Applicant: K.H.S. MUSICAL INSTRUMENT CO., LTD.Inventor: Shih Hao TSENG
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Patent number: 8586155Abstract: A display device includes a display panel and at least one driving chip. The display panel has a display region and a non-display region and includes a pixel array, a plurality of pads, a passivation layer, and a plurality of conductive patterns. The pixel array is located in the display region. The pads are located in the non-display region and electrically connected to the pixel array. The passivation layer is located on the pads and has a plurality of through holes. Each of the conductive patterns covers one of the pads and is electrically connected to the pad through at least one of the through holes. A material of the conductive patterns includes a polymer conductive material. The driving chip is located on the display panel and electrically connected to the pads of the display panel.Type: GrantFiled: February 18, 2011Date of Patent: November 19, 2013Assignee: Au Optronics CorporationInventors: Shih-Hao Tseng, Shih-Hsing Hung, Chih-Jen Hu