Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.

Abstract: A training data processing method and an electronic device are provided. The method includes: obtaining medical history data including at least one first disease suffered by a user; setting a plurality of disease types according to a target disease; setting a time interval; obtaining at least one second disease in the time interval from the medical history data; performing a pre-processing operation on the second disease according to the disease types to obtain processed data; and inputting the processed data to a neural network to train the neural network.

Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.

Abstract: A lighting device includes a light board and a light dimmer circuit. The light board includes multiple first light emitting elements and second light emitting elements. The first light emitting elements are disposed in a first area of the light board. The second light emitting elements are disposed in a second area of the light board. The light dimmer circuit is configured to drive the second light emitting elements to generate flickering lights from the second area of the light board, and is configured to drive the first light emitting elements to generate non-flickering lights from the first area of the light board.

Abstract: The present disclosure provides an image sensing module including a main board and an image sensor. The main board has a first surface and a second surface opposite to each other. The image sensor is disposed on the first surface of the main board and includes a plurality of isolation structures and a photoelectric conversion element between the plurality of isolation structures. A first angle is provided between a light incident surface of the photoelectric conversion element and the first surface of the main board, and a second angle is provided between a light beam incident to the light incident surface of the photoelectric conversion element and a normal vector of the light incident surface. The second angle is about equal to the Brewster angle at the interface of the light beam incident to the light incident surface.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first well region disposed within a substrate and comprising a first doping type. A conductive structure overlies the first well region. A pair of first doped regions is disposed within the first well region on opposing sides of the conductive structure. The pair of first doped regions comprise a second doping type opposite the first doping type. A pair of second doped regions is disposed within the first well region on the opposing sides of the conductive structure. The pair of second doped regions comprise the second doping type and are laterally offset from the pair of first doped regions by a non-zero distance.

Abstract: Embodiments described herein relate to methods of forming layers using maskless based lithography. In these embodiments, the methods implement ladders of dose change such that a geometric shape can be divided into overlaying sections. The overlaying sections can include a different dose of each section such that taper control can be achieved. The taper can be achieved by manipulating the geometry “mask data” into overlaying sections that are exposed by various doses controlled by pixel blending (PB) exposure techniques. To perform the methods described herein, a maskless lithography tool is used. The maskless lithography tool includes a controller that performs software based “mask data” manipulation.

Abstract: Embodiments described herein relate to methods of forming layers using maskless based lithography. In these embodiments, the methods implement ladders of dose change such that a geometric shape can be divided into overlaying sections. The overlaying sections can include a different dose of each section such that taper control can be achieved. The taper can be achieved by manipulating the geometry “mask data” into overlaying sections that are exposed by various doses controlled by pixel blending (PB) exposure techniques. To perform the methods described herein, a maskless lithography tool is used. The maskless lithography tool includes a controller that performs software based “mask data” manipulation.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region. A second memory active region is disposed within the second well region and is laterally offset from the first memory active region by a non-zero distance.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a target layer on the substrate, and a hard mask layer doped with a group IV-A element on the target layer. The number of sp3 orbital bonds in the hard mask layer is greater than the number of sp2 orbital bonds.

Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electrode from the CESL structure, the insulating stack including a first resist protective layer disposed over the floating gate electrode, a second resist protective layer disposed over the first resist protective layer, and an insulating layer separating the first resist protective layer from the second resist protective layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region.

Abstract: An integrated chip includes a first well region, second well region, and third well region disposed within a substrate. The second well region is laterally between the first and third well regions. An isolation structure is disposed within the substrate and laterally surrounds the first, second, and third well regions. A floating gate overlies the substrate and laterally extends from the first well region to the third well region. A dielectric structure is disposed under the floating gate. A bit line write region is disposed within the second well region and includes source/drain regions disposed on opposite sides of the floating gate. A bit line read region is disposed within the second well region, is laterally offset from the bit line write region by a non-zero distance, and includes source/drain regions disposed on the opposite sides of the floating gate.

Abstract: A memory cell may include first and second storage transistors. A first capacitor includes a first capacitor active region disposed within a substrate and a capacitor plate comprised of a first floating gate portion of a floating gate. A second capacitor includes a second capacitor active region disposed within the substrate and a capacitor plate comprised of a second floating gate portion of the floating gate. The first storage transistor includes source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate. The second storage transistor includes source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate. The bit line read and write regions are offset from one another by a non-zero distance.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including first and second storage transistors. A first capacitor includes a first capacitor active region disposed within a substrate and a capacitor plate comprised of a first floating gate portion of a floating gate. A second capacitor includes a second capacitor active region disposed within the substrate and a capacitor plate comprised of a second floating gate portion of the floating gate. The first storage transistor includes source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate. The second storage transistor includes source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate. The bit line read and write regions are offset from one another by a non-zero distance.