Patents by Inventor Shih-Hsun Chang
Shih-Hsun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11404555Abstract: A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.Type: GrantFiled: May 4, 2020Date of Patent: August 2, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jen-Hsiang Lu, Tsung-Han Tsai, Shih-Hsun Chang
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Patent number: 11348841Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate, wherein the gate stack has a first portion and a second portion under the first portion, and the first portion is wider than the second portion. The semiconductor device structure includes a first spacer and a second spacer over opposite sides of the gate stack. The first spacer has a first upper portion and a first lower portion, the second spacer has a second upper portion and a second lower portion. The first spacer has a first recess, the first upper portion is between the first recess and the gate stack, the first lower portion is under the first recess, and the first recess has a first inner wall facing away from the gate stack.Type: GrantFiled: August 28, 2020Date of Patent: May 31, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Pei-Lin Wu, Yi-Ren Chen, Shih-Hsun Chang
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Patent number: 11295990Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.Type: GrantFiled: January 6, 2020Date of Patent: April 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
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Publication number: 20220102147Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.Type: ApplicationFiled: December 13, 2021Publication date: March 31, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Yu CHEN, Yu-Chi LU, Chih-Pin TSAO, Shih-Hsun CHANG
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Publication number: 20220069098Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a semiconductor substrate. The semiconductor device structure also includes a gate dielectric layer formed between the gate electrode layer and the semiconductor substrate. In addition, the semiconductor device structure includes a first gate spacer having a hydrophobic surface that covers a first sidewall of the gate electrode layer. The first sidewall of the gate electrode layer extends along a first sidewall of the gate dielectric layer, so that the first sidewall of the gate dielectric layer is separated from the hydrophobic surface of the first gate spacer.Type: ApplicationFiled: November 10, 2021Publication date: March 3, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Han TSAI, Jen-Hsiang LU, Shih-Hsun CHANG
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Patent number: 11201059Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.Type: GrantFiled: December 2, 2019Date of Patent: December 14, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
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Patent number: 11177361Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed across the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below a portion of the gate structure and two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. In addition, the first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall, and the gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.Type: GrantFiled: June 1, 2020Date of Patent: November 16, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Han Tsai, Jen-Hsiang Lu, Shih-Hsun Chang
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Publication number: 20210328058Abstract: A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which defines a dummy gate dielectric region. A portion of the dielectric layer not included in the dummy gate dielectric region is etched to form a dielectric etch back region. A spacer element is formed on a portion of the dielectric etch back region, which abuts the dummy gate structure, and defines a spacer dielectric region A height of the dummy gate dielectric region is greater than the height of the spacer dielectric region. A recessed portion is formed in the substrate, over which a strained material is selectively grown to form a strained recessed region adjacent the spacer dielectric region. The dummy gate structure and the dummy gate dielectric region are removed. A gate electrode layer and a gate dielectric layer are formed.Type: ApplicationFiled: June 28, 2021Publication date: October 21, 2021Inventors: Chun-Sheng LIANG, Shih-Hsun CHANG
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Publication number: 20210313328Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Inventors: Shun-Jang LIAO, Chia-Chun LIAO, Shu-Hui WANG, Shih-Hsun CHANG
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Patent number: 11049970Abstract: A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which defines a dummy gate dielectric region. A portion of the dielectric layer not included in the dummy gate dielectric region is etched to form a dielectric etch back region. A spacer element is formed on a portion of the dielectric etch back region, which abuts the dummy gate structure, and defines a spacer dielectric region A height of the dummy gate dielectric region is greater than the height of the spacer dielectric region. A recessed portion is formed in the substrate, over which a strained material is selectively grown to form a strained recessed region adjacent the spacer dielectric region. The dummy gate structure and the dummy gate dielectric region are removed. A gate electrode layer and a gate dielectric layer are formed.Type: GrantFiled: August 13, 2018Date of Patent: June 29, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Sheng Liang, Shih-Hsun Chang
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Patent number: 11043491Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.Type: GrantFiled: December 20, 2019Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shun-Jang Liao, Chia-Chun Liao, Shu-Hui Wang, Shih-Hsun Chang
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Publication number: 20210013205Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.Type: ApplicationFiled: September 28, 2020Publication date: January 14, 2021Inventors: Chia-Chun LIAO, Chun-Sheng LIANG, Shu-Hui WANG, Shih-Hsun CHANG, Yi-Jen CHEN
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Publication number: 20200395253Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate, wherein the gate stack has a first portion and a second portion under the first portion, and the first portion is wider than the second portion. The semiconductor device structure includes a first spacer and a second spacer over opposite sides of the gate stack. The first spacer has a first upper portion and a first lower portion, the second spacer has a second upper portion and a second lower portion. The first spacer has a first recess, the first upper portion is between the first recess and the gate stack, the first lower portion is under the first recess, and the first recess has a first inner wall facing away from the gate stack.Type: ApplicationFiled: August 28, 2020Publication date: December 17, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Heng TSAI, Chun-Sheng LIANG, Pei-Lin WU, Yi-Ren CHEN, Shih-Hsun CHANG
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Patent number: 10825813Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.Type: GrantFiled: July 30, 2018Date of Patent: November 3, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shun-Jang Liao, Chia-Chun Liao, Shu-Hui Wang, Shih-Hsun Chang
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Patent number: 10790283Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.Type: GrantFiled: April 29, 2019Date of Patent: September 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Chun Liao, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Yi-Jen Chen
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Publication number: 20200303511Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed across the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below a portion of the gate structure and two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. In addition, the first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall, and the gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.Type: ApplicationFiled: June 1, 2020Publication date: September 24, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Han TSAI, Jen-Hsiang LU, Shih-Hsun CHANG
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Patent number: 10763178Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack has a first upper portion and a first lower portion, and the first upper portion is wider than the first lower portion. The semiconductor device structure includes a spacer layer surrounding the gate stack. The spacer layer has a second upper portion and a second lower portion. The second upper portion is thinner than the second lower portion.Type: GrantFiled: November 20, 2018Date of Patent: September 1, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Pei-Lin Wu, Yi-Ren Chen, Shih-Hsun Chang
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Publication number: 20200266282Abstract: A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.Type: ApplicationFiled: May 4, 2020Publication date: August 20, 2020Inventors: Jen-Hsiang Lu, Tsung-Han Tsai, Shih-Hsun Chang
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Patent number: 10672879Abstract: A method of forming a semiconductor device structure is provided. The method includes forming an isolation feature over a semiconductor substrate. The semiconductor substrate includes a fin structure over the isolation feature. Two opposing spacer elements are formed over the isolation feature and across the fin structure so as to define a gate opening. The gate opening exposes the fin structure and the isolation feature and inner sidewalls of the gate opening have carbon-containing hydrophobic surfaces. A gate structure is formed in the gate opening with the carbon-containing hydrophobic surfaces.Type: GrantFiled: July 30, 2018Date of Patent: June 2, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Han Tsai, Jen-Hsiang Lu, Shih-Hsun Chang
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Publication number: 20200152521Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.Type: ApplicationFiled: January 6, 2020Publication date: May 14, 2020Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang