Patents by Inventor Shih-Jye Shen
Shih-Jye Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8497172Abstract: A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.Type: GrantFiled: July 16, 2012Date of Patent: July 30, 2013Assignee: eMemory Technology Inc.Inventors: Ching-Hsiang Hsu, Ching-Sung Yang, Shih-Jye Shen
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Patent number: 8466519Abstract: A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.Type: GrantFiled: August 6, 2009Date of Patent: June 18, 2013Assignee: eMemory Technology Inc.Inventors: Ching-Hsiang Hsu, Ching-Sung Yang, Shih-Jye Shen
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Publication number: 20120276700Abstract: A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.Type: ApplicationFiled: July 16, 2012Publication date: November 1, 2012Inventors: Ching-Hsiang Hsu, Ching-Sung Yang, Shih-Jye Shen
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Patent number: 7960792Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.Type: GrantFiled: November 11, 2010Date of Patent: June 14, 2011Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Publication number: 20110057243Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.Type: ApplicationFiled: November 11, 2010Publication date: March 10, 2011Applicant: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Patent number: 7903472Abstract: An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive type drain region, and a second conductive type source region. In operating such a non-volatile memory, voltages are applied to the gate, the second conductive type drain region, the second conductive type source region and the first conductive type silicon body layer beneath the gate, to inject electrons or holes in to the charge storage structure or evacuate the electrons from the charge storage structure by a method selected from a group consisting of channel hot carrier injection, source side injection, band-to-band tunnelling hot carrier injection and Fowler-Nordheim (F-N) tunnelling.Type: GrantFiled: September 24, 2009Date of Patent: March 8, 2011Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Publication number: 20110031560Abstract: A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.Type: ApplicationFiled: August 6, 2009Publication date: February 10, 2011Inventors: Ching-Hsiang Hsu, Ching-Sung Yang, Shih-Jye Shen
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Patent number: 7855417Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the conductive type silicon body layer beneath the gate.Type: GrantFiled: August 3, 2007Date of Patent: December 21, 2010Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Patent number: 7768059Abstract: A non-volatile single-poly memory device is disclosed. The non-volatile single-poly memory device includes two mirror symmetric unit cells, which is capable of providing improved data correctness. Further, the non-volatile single-poly memory device is operated at low voltages and is fully compatible with logic processes.Type: GrantFiled: March 26, 2007Date of Patent: August 3, 2010Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Shih-Chen Wang, Ming-Chou Ho, Shih-Jye Shen
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Patent number: 7682908Abstract: A non-volatile memory including a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, and a second gate structure is disclosed. The doped regions are disposed in the substrate and the second doped region is disposed between the first doped region and the third doped region. The first gate structure is disposed on the substrate between the first doped region and the second doped region. The second gate structure is disposed on the substrate between the second doped region and the third doped region, and comprises a tunneling dielectric layer, a charge trapping structure and a gate from the bottom up.Type: GrantFiled: October 28, 2005Date of Patent: March 23, 2010Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Publication number: 20100014359Abstract: An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive type drain region, and a second conductive type source region. In operating such a non-volatile memory, voltages are applied to the gate, the second conductive type drain region, the second conductive type source region and the first conductive type silicon body layer beneath the gate, to inject electrons or holes in to the charge storage structure or evacuate the electrons from the charge storage structure by a method selected from a group consisting of channel hot carrier injection, source side injection, band-to-band tunnelling hot carrier injection and Fowler-Nordheim (F-N) tunnelling.Type: ApplicationFiled: September 24, 2009Publication date: January 21, 2010Applicant: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Patent number: 7551494Abstract: A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a P+ source doping region and a P+ drain doping region. The ONO layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.Type: GrantFiled: May 22, 2008Date of Patent: June 23, 2009Assignee: eMemory Technology Inc.Inventors: Chrong-Jung Lin, Hsin-Ming Chen, Shih-Jye Shen, Ya-Chin King, Ching-Hsiang Hsu
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Publication number: 20080293199Abstract: A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a P+ source doping region and a P+ drain doping region. The ONO layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.Type: ApplicationFiled: May 22, 2008Publication date: November 27, 2008Inventors: Chrong-Jung Lin, Hsin-Ming Chen, Shih-Jye Shen, Ya-Chin King, Ching-Hsiang Hsu
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Patent number: 7447082Abstract: A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a dielectric stack layer on sidewalls of the gate, a source doping region and a drain doping region. The dielectric stack layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the ion well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.Type: GrantFiled: November 1, 2006Date of Patent: November 4, 2008Assignee: eMemory Technology Inc.Inventors: Shih-Chen Wang, Hsin-Ming Chen, Chun-Hung Lu, Ming-Chou Ho, Shih-Jye Shen, Ching-Hsiang Hsu
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Patent number: 7433243Abstract: A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.Type: GrantFiled: November 9, 2006Date of Patent: October 7, 2008Assignee: eMemory Technology Inc.Inventors: Shih-Chen Wang, Hsin-Ming Chen, Chun-Hung Lu, Ming-Chou Ho, Shih-Jye Shen, Ching-Hsiang Hsu
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Patent number: 7417897Abstract: A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N source region. N channel is defined between the N drain region and N source region. The NVM cell is programmed by breaking down the gate dielectric layer. To read the NVM cell, a positive voltage is provided to N drain region, a positive voltage is provided to the gate, and grounding the N source region and the P substrate.Type: GrantFiled: January 23, 2007Date of Patent: August 26, 2008Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Shih-Jye Shen, Ching-Hsiang Hsu
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Publication number: 20080138956Abstract: A semiconductor device formed on a first conductive type substrate is provided. The device includes a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region and the second conductive type source region are formed in the first conductive type substrate at both sides of the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate between the gate and the second conductive type source region.Type: ApplicationFiled: December 21, 2007Publication date: June 12, 2008Applicant: EMEMORY TECHNOLOGY INC.Inventors: Shih-Chen Wang, Hsin-Ming Chen, Chun-Hung Lu, Ming-Chou Ho, Shih-Jye Shen, Ching-Hsiang Hsu
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Publication number: 20080031038Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.Type: ApplicationFiled: August 3, 2007Publication date: February 7, 2008Applicant: EMEMORY TECHNOLOGY INC.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Publication number: 20070296034Abstract: A single-poly SOI memory cell includes a PMOS select transistor serially connected with a floating-gate PMOS transistor on an SOI substrate. The PMOS select transistor includes a select gate, a P+ source region and a P+ drain/source region. The floating-gate PMOS transistor includes a floating gate, a P+ drain region and the P+ drain/source region, wherein the P+ drain/source region is shared by the PMOS select transistor and the floating-gate PMOS transistor. A floating first N+ doping region is disposed within the P+ drain/source region. The first N+ doping region, which is adjacent to the floating gate, acts as a source-tie pick-up.Type: ApplicationFiled: June 8, 2007Publication date: December 27, 2007Inventors: Hsin-Ming Chen, Shih-Chen Wang, Ming-Chou Ho, Shih-Jye Shen
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Publication number: 20070296018Abstract: A non-volatile single-poly memory device is disclosed. The non-volatile single-poly memory device includes two mirror symmetric unit cells, which is capable of providing improved data correctness. Further, the non-volatile single-poly memory device is operated at low voltages and is fully compatible with logic processes.Type: ApplicationFiled: March 26, 2007Publication date: December 27, 2007Inventors: Hsin-Ming Chen, Shih-Chen Wang, Ming-Chou Ho, Shih-Jye Shen