Patents by Inventor Shih Kuei Yen

Shih Kuei Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11069690
    Abstract: A flash includes a substrate comprising an active region and two electron storage structures disposed at two sides of the active region, wherein each of the electron storage structures comprises a silicon oxide/silicon nitride/silicon oxide composite layer. A buried gate is embedded in the active region, wherein the buried gate only consists of a control gate and a gate dielectric layer, and the gate dielectric layer is formed by a single material. Two source/drain doping regions are disposed in the active region at two sides of the buried gate.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 20, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Shih-Kuei Yen, Li-Wei Liu, Le-Tien Jung, Hung-Lin Shih, Hsuan-Tung Chu, Ming-Che Li, Guan-Yi Liou, Huai-Jin Hsing
  • Publication number: 20200083228
    Abstract: A flash includes a substrate comprising an active region and two electron storage structures disposed at two sides of the active region, wherein each of the electron storage structures comprises a silicon oxide/silicon nitride/silicon oxide composite layer. A buried gate is embedded in the active region, wherein the buried gate only consists of a control gate and a gate dielectric layer, and the gate dielectric layer is formed by a single material. Two source/drain doping regions are disposed in the active region at two sides of the buried gate.
    Type: Application
    Filed: September 28, 2018
    Publication date: March 12, 2020
    Inventors: Shih-Kuei Yen, Li-Wei Liu, Le-Tien Jung, Hung-Lin Shih, Hsuan-Tung Chu, Ming-Che Li, Guan-Yi Liou, Huai-Jin Hsing
  • Patent number: 10497704
    Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 3, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ger-Pin Lin, Kuan-Chun Lin, Chi-Mao Hsu, Shu-Yen Chan, Shih-Fang Tzou, Tsuo-Wen Lu, Tien-Chen Chan, Feng-Yi Chang, Shih-Kuei Yen, Fu-Che Lee
  • Publication number: 20190164977
    Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.
    Type: Application
    Filed: December 20, 2018
    Publication date: May 30, 2019
    Inventors: Ger-Pin Lin, Kuan-Chun Lin, Chi-Mao Hsu, Shu-Yen Chan, Shih-Fang Tzou, Tsuo-Wen Lu, Tien-Chen Chan, Feng-Yi Chang, Shih-Kuei Yen, Fu-Che Lee
  • Publication number: 20190067293
    Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.
    Type: Application
    Filed: September 21, 2017
    Publication date: February 28, 2019
    Inventors: Ger-Pin Lin, Kuan-Chun Lin, Chi-Mao Hsu, Shu-Yen Chan, Shih-Fang Tzou, Tsuo-Wen Lu, Tien-Chen Chan, Feng-Yi Chang, Shih-Kuei Yen, Fu-Che Lee
  • Patent number: 10217750
    Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: February 26, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ger-Pin Lin, Kuan-Chun Lin, Chi-Mao Hsu, Shu-Yen Chan, Shih-Fang Tzou, Tsuo-Wen Lu, Tien-Chen Chan, Feng-Yi Chang, Shih-Kuei Yen, Fu-Che Lee
  • Patent number: 5746928
    Abstract: A method of cleaning an electrostatic chuck of a plasma etching apparatus wherein a dummy wafer is placed on the chuck, the chamber evacuated, and an RF voltage applied that is greater than the normal RF voltage used to etch.
    Type: Grant
    Filed: June 3, 1996
    Date of Patent: May 5, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd
    Inventors: Shih Kuei Yen, Po-Tao Chu, Kuang-Hui Chang