Abstract: A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.

Abstract: A PUF generator includes a difference generator circuit with first and second transistors having a first predetermined VT. The difference generator circuit is configured to provide a first output signal for generating a PUF signature based on respective turn on times of the first and second transistors. An amplifier includes a plurality of transistors having a second predetermined VT. The amplifier is configured to receive the first output signal and output the PUF signature.

Abstract: A memory circuit includes a first word line, a first and second bit line, a first and second inverter, a P-type pass gate transistor and a pre-charge circuit. The first word line extends in a first direction. The first and second bit line extend in a second direction. The first inverter has a first storage node coupled to the second inverter. The second inverter has a second storage node coupled to the first inverter, and is not coupled to the second bit line. The P-type pass gate transistor is coupled between the first storage node and the first bit line. The pre-charge circuit is coupled to the first or second bit line, and is configured to charge the first or second bit line to a pre-charge voltage responsive to a first signal. The pre-charge voltage is between a voltage of a first logical level and a second logical level.

Abstract: A method of operating an integrated circuit includes writing data to each memory cell in a first memory cell array, powering off the integrated circuit, powering on the integrated circuit, reading data from each memory cell in the first memory cell array in response to powering on the integrated circuit, and determining whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array. The integrated circuit includes a first memory cell array.

Abstract: A method of writing data to a memory array of three-terminal memory cells includes simultaneously programming a first subset of memory cells in a first column of the memory array to a first logic level by activating a first select line of the first column and a first bit line of the first column, and simultaneously programming a second subset of memory cells in the first column to the first logic level by activating the first select line and a second bit line of the first column.

Abstract: A circuit includes a memory array, a control circuit configured to identify an address of a first row containing a weak cell, and store corresponding address information in a storage device, and an address decoding circuit including NAND pairs, inverter pairs, and a logic tree. Each NAND pair receives corresponding bits of the address information and the address of the first row and corresponding inverted bits of the address information and the address of the first row inverted by corresponding inverter pairs, and output terminals of the NAND pairs are connected to the logic tree. The logic tree matches the address information with the address of the first row based on output logic levels from the NAND pairs and, in response to the corresponding address information matching the address of the first row, activates a second row of the memory array simultaneously with the first row being activated.

Abstract: The present disclosure describes an embodiment of a thin film transistor based temperature sensor circuit. The thin film transistor based temperature sensor circuit includes a first frequency generator with thin film transistors, a second frequency generator with complementary metal oxide semiconductor transistors, first and second counter devices, and a processor device. The first and second counter devices are configured to count a number of first pulses and a number of second pulses from the first frequency generator and second frequency generator, respectively. The processor device is configured to determine a frequency based on the number of first and second pulses.

Abstract: A memory device includes a multi-layer stack, a plurality of channel layers and a plurality of ferroelectric layers. The multi-layer stack is disposed on a substrate and includes a plurality of gate layers and a plurality of dielectric layers stacked alternately. The plurality of channel layers penetrate through the multi-layer stack and are laterally spaced apart from each other, wherein the plurality of channel layers include a first channel layer and a second channel layer, and a first electron mobility of the first channel layer is different from a second electron mobility of the second channel layer. Each of the plurality of channel layers are spaced apart from the multi-layer stack by one of the plurality of ferroelectric layers, respectively.

Abstract: Disclosed is a device and method to secure software update information for authorized entities. In one embodiment, a device for receiving secured software update information from a server, the device includes: a physical unclonable function (PUF) information generator, comprising a PUF cell array, configured to generate PUF information, wherein the PUF information comprises at least one PUF response output, wherein the at least one PUF response output is used to encrypt the software update information on the server so as to generate encrypted software update information; a first encrypter, configured to encrypt the PUF information from the PUF information generator using one of at least one public key from the server so as to generate encrypted PUF information; and a second encrypter, configured to decrypt the encrypted software update information using one of the at least one PUF response output so as to obtain the software update information.

Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

Abstract: An integrated circuit (IC) is provided. The IC includes a cache memory divided into a plurality of groups and an address decoder. The groups are assigned in rotation for a plurality of time periods. Each group is assigned in a corresponding single one of the time periods. The address decoder is configured to obtain a set address according to an access address and provide a physical address according to the set address. When the access address corresponds to a first group, the physical address is different from the set address. When the access address corresponds to the groups other than the first group, the physical address is the same as the set address. The sets of the first group that is assigned in a first time period are not overlapping with the sets of other first groups assigned in the time periods other than the first time period.

Abstract: A memory device is described, including a command decoder configured to receive a copy command to copy data stored in a first memory location to a second memory location without transmitting the data to an external controller, a memory array electrically connected to the command decoder and including a plurality of memory locations including the first memory location and the second memory location, a data line electrically connected to the memory array and configured to receive, from the first memory location, the data to be transmitted to the second memory location through the same data line, and an output buffer configured to store the data received from the first memory location through the data line to be written into the second memory location without transmitting the data to the external controller.

Abstract: Disclosed is a physical unclonable function generator circuit and testing method.

Abstract: Disclosed herein are related to operating a memory system including memory banks and buffers. Each buffer may perform a write process to write data to a corresponding memory bank. In one aspect, the memory system includes a buffer controller including a queue register, a first pointer register, a second pointer register, and a queue controller. In one aspect, the queue register includes entries, where each entry may store an address of a corresponding memory bank. The first pointer register may indicate a first entry storing an address of a memory bank, on which the write process is predicted to be completed next. The second pointer register may indicate a second entry to be updated. The queue controller may configure the queue register according to the first pointer register and the second pointer register, and configure one or more buffers to perform the write process, according to the entries.

Abstract: A PUF generator includes a difference generator circuit with first and second transistors having a first predetermined VT. The difference generator circuit is configured to provide a first output signal for generating a PUF signature based on respective turn on times of the first and second transistors. An amplifier includes a plurality of transistors having a second predetermined VT. The amplifier is configured to receive the first output signal and output the PUF signature.

Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.

Abstract: Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. One or more activation signals are provided to a PUF cell under a plurality of conditions. A PUF cell output provided by the PUF cell under each of the plurality of conditions is determined. A determination is made of a number of times the PUF cell output of the PUF cell is consistent. And a device classification value is determined based on the determined number of times for a plurality of PUF cells.

Abstract: Disclosed is a device and method to secure software update information for authorized entities. In one embodiment, a device for receiving secured software update information from a server, the device includes: a physical uncolonable function (PUF) information generator, comprising a PUF cell array, configured to generate PUF information, wherein the PUF information comprises at least one PUF response output, wherein the at least one PUF response output is used to encrypt the software update information on the server so as to generate encrypted software update information; a first encrypter, configured to encrypt the PUF information from the PUF information generator using one of at least one public key from the server so as to generate encrypted PUF information; and a second encrypter, configured to decrypt the encrypted software update information using one of the at least one PUF response output so as to obtain the software update information.

Abstract: A physically unclonable function (PUF) cell array includes a first PUF cell in a first column in a first direction, and a first row in a second direction, and a second PUF cell in a second row in the second direction. The first PUF cell includes a first set of conductive structures extending in the first and second direction, being on a first metal layer, and including a first and a second conductive structure extending in the first direction. The second PUF cell includes a second set of conductive structures extending in the first direction and second direction, being on the first metal layer and including a third and a fourth conductive structure extending in the first direction. The first and third conductive structures, or the second and fourth conductive structures are symmetric to each other with respect to a central line of the first and second PUF cells.

Abstract: A memory device includes: a memory device configured to store data bits to be written to the memory device; and a memory controller. The memory controller includes: a first level error correction code (ECC) circuit coupled to the memory device, wherein the first level ECC circuit is configured to generate a first plurality of first level check bits corresponding to the data bits based on a first error detection scheme; and a second level ECC circuit coupled to the memory device, wherein the second level ECC circuit is configured to generate a second plurality of second level check bits corresponding to both the data bits and the first plurality of first level check bits based on a first error correction scheme.