Patents by Inventor Shih-Ming Kuo
Shih-Ming Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10365738Abstract: A touch display apparatus includes a touch electrode structure and a display assembly. The touch electrode structure senses touch operations on the touch display apparatus. The display assembly displays images of the touch display apparatus. The display assembly includes a polarizer, a first substrate, a color filter, and a second substrate, arranged in that order. The touch electrode structure is sandwiched between the polarizer and the first substrate. The touch electrode structure comprises a first sensing electrode layer. The first sensing electrode is formed on a surface of the first substrate opposite to the color filter.Type: GrantFiled: May 8, 2016Date of Patent: July 30, 2019Assignees: INTERFACE OPTOELECTRONIC (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITEDInventors: Yue-Feng Yang, Wei-Chung Chuang, Yen-Heng Huang, Shih-Ming Kuo
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Patent number: 9747404Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.Type: GrantFiled: July 23, 2015Date of Patent: August 29, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Ming Kuo, Ming-Jui Chen, Te-Hsien Hsieh, Ping-I Hsieh, Jing-Yi Lee, Yan-Chun Chen
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Publication number: 20170024506Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.Type: ApplicationFiled: July 23, 2015Publication date: January 26, 2017Inventors: Shih-Ming Kuo, Ming-Jui Chen, Te-Hsien Hsieh, Ping-I Hsieh, Jing-Yi Lee, Yan-Chun Chen
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Patent number: 9503554Abstract: A portable electronic apparatus includes a first touch-sensing substrate, a camera module, transmission routes, a flexible printed circuit, and a main board. The first touch-sensing substrate has an active area and a peripheral area surrounding the active area. The camera module is connected to a second connecting area of the peripheral area. At least one of the transmission routes connects between a first connecting area and the second connecting area of the peripheral area, and rest of the transmission routes respectively connect between the active area and the first connecting area. The flexible printed circuit connects to the first connecting area. The flexible printed circuit includes a touch-sensor driver. The touch-sensor driver is electrically connected to at least part of the transmission routes. The main board includes a connector. The connector is connected with an end of the flexible printed circuit.Type: GrantFiled: April 10, 2016Date of Patent: November 22, 2016Assignees: INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITEDInventors: Shih-Ming Kuo, Yue-Feng Yang, Wei-Chung Chuang, Yen-Heng Huang
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Publication number: 20160328063Abstract: A touch display apparatus includes a touch electrode structure and a display assembly. The touch electrode structure senses touch operations on the touch display apparatus. The display assembly displays images of the touch display apparatus. The display assembly includes a polarizer, a first substrate, a color filter, and a second substrate, arranged in that order. The touch electrode structure is sandwiched between the polarizer and the first substrate. The touch electrode structure comprises a first sensing electrode layer. The first sensing electrode is formed on a surface of the first substrate opposite to the color filter.Type: ApplicationFiled: May 8, 2016Publication date: November 10, 2016Inventors: YUE-FENG YANG, WEI-CHUNG CHUANG, YEN-HENG HUANG, SHIH-MING KUO
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Publication number: 20150036116Abstract: An aperture is configured to be disposed between an illumination source and a semiconductor substrate in a photolithography system. The aperture includes a light-transmission portion with a non-planar thickness profile to compensate the discrepancy of wave-fronts of the light beams of different orders.Type: ApplicationFiled: August 2, 2013Publication date: February 5, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Te-Hsien Hsieh, Shih-Ming Kuo, Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee
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Patent number: 8806391Abstract: A method of optical proximity correction (OPC) includes the following steps. At first, a layout pattern is provided to a computer system. Subsequently, the layout pattern is classified into at least a first region and at least a second region. Then, several iterations of OPC calculations are performed to the layout pattern, and a total number of OPC calculations performed in the first region is substantially larger than a total number of OPC calculations performed in the second region. Afterwards, a corrected layout pattern is outputted through the computer system onto a mask.Type: GrantFiled: July 31, 2012Date of Patent: August 12, 2014Assignee: United Microelectronics Corp.Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Shih-Ming Kuo, Jing-Yi Lee
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Patent number: 8745547Abstract: A method for making a photomask layout is disclosed. A graphic data of a photomask is provided. A first correction step is performed to the graphic data. A first verification step is performed to all of the graphic data which has been subjected to the first correction step, wherein at least one failed pattern not passing the first verification step is found. A second correction step is performed to the at least one failed pattern, so as to obtain at least one modified pattern. A second verification step is performed only to at least one buffer region covering the at least one modified pattern, wherein the buffer region has an area less than a whole area of the photomask. Besides, each of the first correction step, the first verification step, the second correction step and the second verification step is executed by a computer.Type: GrantFiled: July 11, 2013Date of Patent: June 3, 2014Assignee: United Microelectronics Corp.Inventors: Shih-Ming Kuo, Ming-Jui Chen, Te-Hsien Hsieh, Cheng-Te Wang, Jing-Yi Lee
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Publication number: 20140040837Abstract: A method of optical proximity correction (OPC) includes the following steps. At first, a layout pattern is provided to a computer system. Subsequently, the layout pattern is classified into at least a first region and at least a second region. Then, several iterations of OPC calculations are performed to the layout pattern, and a total number of OPC calculations performed in the first region is substantially larger than a total number of OPC calculations performed in the second region. Afterwards, a corrected layout pattern is outputted through the computer system onto a mask.Type: ApplicationFiled: July 31, 2012Publication date: February 6, 2014Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Shih-Ming Kuo, Jing-Yi Lee
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Patent number: 8383299Abstract: A double patterning mask set includes a first mask having a first set of via patterns, and a second mask having a second set of via patterns. The first set of via patterns includes at least two via patterns arranged along a diagonal direction, each of the at least two via patterns has at least a truncated corner. The first set of via patterns and the second set of via patterns are interlacedly arranged along a horizontal direction and a vertical direction.Type: GrantFiled: May 17, 2011Date of Patent: February 26, 2013Assignee: United Microelectronics Corp.Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Shih-Ming Kuo, Ping-I Hsieh, Cheng-Te Wang, Jing-Yi Lee
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Publication number: 20120295186Abstract: A double patterning mask set includes a first mask having a first set of via patterns, and a second mask having a second set of via patterns. The first set of via patterns includes at least two via patterns arranged along a diagonal direction, each of the at least two via patterns has at least a truncated corner. The first set of via patterns and the second set of via patterns are interlacedly arranged along a horizontal direction and a vertical direction.Type: ApplicationFiled: May 17, 2011Publication date: November 22, 2012Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Shih-Ming Kuo, Ping-I Hsieh, Cheng-Te Wang, Jing-Yi Lee
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Patent number: 8042069Abstract: A method to selectively amend a layout pattern is disclosed. First, a layout pattern including at least a first group and a second group is provided, wherein each one of the first group and the second group respectively includes multiple members. Second, a simulation procedure and an amendment procedure are respectively performed on all the members of the first group and the second group to obtain an amended first group and an amended second group. Then, the amended first group and the amended second group are verified as being on target or not. Afterwards, the layout pattern including the on target amended first group and the on target amended second group is output.Type: GrantFiled: August 7, 2008Date of Patent: October 18, 2011Assignee: United Microelectronics Corp.Inventors: Yu-Shiang Yang, Te-Hung Wu, Yung-Feng Cheng, Chuen Huei Yang, Hsiang-Yun Huang, Hui-Fang Kuo, Shih-Ming Kuo, Lun-Hung Chen
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Publication number: 20100036644Abstract: A method to selectively amend a layout pattern is disclosed. First, a layout pattern including at least a first group and a second group is provided, wherein each one of the first group and the second group respectively includes multiple members. Second, a simulation procedure and an amendment procedure are respectively performed on all the members of the first group and the second group to obtain an amended first group and an amended second group. Then, the amended first group and the amended second group are verified as being on target or not. Afterwards, the layout pattern including the on target amended first group and the on target amended second group is output.Type: ApplicationFiled: August 7, 2008Publication date: February 11, 2010Inventors: Yu-Shiang Yang, Te-Hung Wu, Yung-Feng Cheng, Chuen Huei Yang, Hsiang-Yun Huang, Hui-Fang Kuo, Shih-Ming Kuo, Lun-Hung Chen