Abstract: Semiconductor device, multi-die packages, and methods of manufacture thereof are described. In an embodiment, a semiconductor device may include: first conductive pillars and second conductive pillars respectively aligned to a first row of first pins and a second row of second pins of a first die, the first pins and the second pins differing in function; a first insulating layer covering surfaces of the first conductive pillars and the second conductive pillars facing away from the first die; first pads disposed on a surface of the first insulating layer facing away from the first die, the first pads substantially aligned to the first conductive pillars; and first traces coupled to the first pads, the first traces extending over a portion of the first insulating layer covering the second conductive pillars.

Abstract: Semiconductor device, multi-die packages, and methods of manufacture thereof are described. In an embodiment, a semiconductor device may include: first conductive pillars and second conductive pillars respectively aligned to a first row of first pins and a second row of second pins of a first die, the first pins and the second pins differing in function; a first insulating layer covering surfaces of the first conductive pillars and the second conductive pillars facing away from the first die; first pads disposed on a surface of the first insulating layer facing away from the first die, the first pads substantially aligned to the first conductive pillars; and first traces coupled to the first pads, the first traces extending over a portion of the first insulating layer covering the second conductive pillars.

Abstract: A package includes a substrate, the substrate having a first side and a second side, the second side being opposite the first side, and a stack of dies on a first side of the substrate. The package further includes a probing pad on the first side of the substrate, the probing pad being electrically coupled to the stack of dies, and a contact pad on the second side of the substrate, the contact pad being electrically coupled to the stack of dies.

Abstract: A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a top surface of the wafer-level package substrate into the wafer-level package substrate. A plurality of dies is bonded over the wafer-level package substrate. The plurality of dies is molded in a molding material to form a wafer-level package, with the wafer-level package including the wafer-level package substrate, the plurality of dies, and the molding material. The carrier is detached from the wafer-level package. The wafer-level package is sawed into a plurality of packages, with each of the plurality of packages including a portion of the wafer-level package substrate and one of the plurality of dies.

Abstract: A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a top surface of the wafer-level package substrate into the wafer-level package substrate. A plurality of dies is bonded over the wafer-level package substrate. The plurality of dies is molded in a molding material to form a wafer-level package, with the wafer-level package including the wafer-level package substrate, the plurality of dies, and the molding material. The carrier is detached from the wafer-level package. The wafer-level package is sawed into a plurality of packages, with each of the plurality of packages including a portion of the wafer-level package substrate and one of the plurality of dies.

Abstract: A method for forming integrated circuit packages is presented. A first plurality of first tier stacks are mounted to the substrate, wherein the substrate has one or more contact pads corresponding to each of the first tier stacks and has one or more probing pads associated with each of the first tier stacks. Each of the first tier stacks is electrically tested to identify known good first tier stacks and known bad first tier stacks. A first plurality of stacking substrates are mounted to the known good first tier stacks, thereby forming a plurality of second tier stacks. Each of the second tier stacks is electrically tested to identify known good second tier stacks and known bad second tier stacks.

Abstract: Semiconductor device, multi-die packages, and methods of manufacture thereof are described. In an embodiment, a semiconductor device may include: first conductive pillars and second conductive pillars respectively aligned to a first row of first pins and a second row of second pins of a first die, the first pins and the second pins differing in function; a first insulating layer covering surfaces of the first conductive pillars and the second conductive pillars facing away from the first die; first pads disposed on a surface of the first insulating layer facing away from the first die, the first pads substantially aligned to the first conductive pillars; and first traces coupled to the first pads, the first traces extending over a portion of the first insulating layer covering the second conductive pillars.

Abstract: A method for forming integrated circuit packages is presented. A first plurality of first tier stacks are mounted to the substrate, wherein the substrate has one or more contact pads corresponding to each of the first tier stacks and has one or more probing pads associated with each of the first tier stacks. Each of the first tier stacks is electrically tested to identify known good first tier stacks and known bad first tier stacks. A first plurality of stacking substrates are mounted to the known good first tier stacks, thereby forming a plurality of second tier stacks. Each of the second tier stacks is electrically tested to identify known good second tier stacks and known bad second tier stacks.

Abstract: A method for forming integrated circuit packages is presented. A first plurality of first tier stacks are mounted to the substrate, wherein the substrate has one or more contact pads corresponding to each of the first tier stacks and has one or more probing pads associated with each of the first tier stacks. Each of the first tier stacks is electrically tested to identify known good first tier stacks and known bad first tier stacks. A first plurality of stacking substrates are mounted to the known good first tier stacks, thereby forming a plurality of second tier stacks. Each of the second tier stacks is electrically tested to identify known good second tier stacks and known bad second tier stacks.

Abstract: This disclosure relates to vaccine formulations comprising an immunogenic composition for inducing antibodies to both S. pneumoniae and N. meningitides in a subject. In a preferred aspect, the immunogenic composition comprises covalently conjugated recombinant PsaA (“rPsaA”) from S. pneumoniae and capsular polysaccharide from N. meningitidis serogroup C. This disclosure further relates to methods for producing the immunogenic composition as well as methods for their use.

Abstract: A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a top surface of the wafer-level package substrate into the wafer-level package substrate. A plurality of dies is bonded over the wafer-level package substrate. The plurality of dies is molded in a molding material to form a wafer-level package, with the wafer-level package including the wafer-level package substrate, the plurality of dies, and the molding material. The carrier is detached from the wafer-level package. The wafer-level package is sawed into a plurality of packages, with each of the plurality of packages including a portion of the wafer-level package substrate and one of the plurality of dies.

Abstract: Methods and apparatus for direct connection to a through via. An apparatus includes a substrate having a front side surface and a back side surface; conductive through vias formed in the substrate and having through via protrusions extending from the back side surface; solder connectors on another device and coupling the another device to the substrate, wherein the solder connectors correspond to the through via protrusions and enclose the through via protrusions to form solder joints; and connectors on the front side surface of the substrate for forming additional electrical connections. Methods include providing a substrate with through vias; thinning the substrate; etching the substrate to create through via protrusions; aligning another device with solder connectors on a surface corresponding to the through via protrusions; placing the solder connectors in contact with the protrusions; and performing a thermal reflow to form solder joints around the through via protrusions.

Abstract: This disclosure relates to vaccine formulations comprising an immunogenic composition for inducing antibodies to both S. pneumoniae and N. meningitides in a subject. In a preferred aspect, the immunogenic composition comprises covalently conjugated recombinant PsaA (“rPsaA”) from S. pneumoniae and capsular polysaccharide from N. meningitidis serogroup C. This disclosure further relates to methods for producing the immunogenic composition as well as methods for their use.

Abstract: A long seeking control method, for an optical information reproduction/recoding system having a lens and a sledge, includes: obtaining a sledge estimation velocity, a sledge estimation displacement, a sledge reference velocity and a first force applied to the sledge; determining to generate the sledge estimation velocity and the sledge estimation displacement in a first open loop control or in a first close loop control based on the sledge estimation velocity; determining to generate the a second force applied to the lens in a second open loop control or in a second close loop control based on the sledge estimation velocity; and pushing the sledge and the lens by the first force and the second force.

Abstract: This disclosure relates to vaccine formulations comprising an immunogenic composition for inducing antibodies to both S. pneumoniae and N. meningitides in a subject. In a preferred aspect, the immunogenic composition comprises covalently conjugated recombinant PsaA (“rPsaA”) from S. pneumoniae and capsular polysaccharide from N. meningitidis serogroup C. This disclosure further relates to methods for producing the immunogenic composition as well as methods for their use.

Abstract: This disclosure relates to vaccine formulations comprising an immunogenic composition for inducing antibodies to both S. pneumoniae and N. meningitides in a subject. In a preferred aspect, the immunogenic composition comprises covalently conjugated recombinant PsaA (“rPsaA”) from S. pneumoniae and capsular polysaccharide from N. meningitidis serogroup C. This disclosure further relates to methods for producing the immunogenic composition as well as methods for their use.

Abstract: A multi-domain vertical alignment liquid crystal display (MVA LCD) has a plurality of pixel electrodes for defining a plurality of pixel units. The pixel units are disposed in matrix arrangement, and each of them has a first electrode, a second electrode, and a third electrode. When a voltage is applied to said pixel electrode, the first electrode and the common electrode have a higher absolute voltage difference than the second electrode and the common electrode. The third electrode and the common electrode have the lowest absolute voltage difference.

Abstract: A multi-domain vertical alignment liquid crystal display (MVA LCD) has a plurality of pixel electrodes for defining a plurality of pixel units. The pixel units are disposed in matrix arrangement, and each of them has a first electrode, a second electrode, and a third electrode. When a voltage is applied to said pixel electrode, the first electrode and the common electrode have a higher absolute voltage difference than the second electrode and the common electrode. The third electrode and the common electrode have the lowest absolute voltage difference.

Abstract: An in-plane switching mode liquid crystal display (IPS-LCD) includes a top substrate and a bottom substrate being in parallel with and opposite to the top substrate, a first electrode and a second electrode elongated along a first direction in an interlaced arrangement, and a plurality of liquid crystal molecules filled in between the top substrate and the bottom substrate. The longitudinal axis of the liquid crystal molecules is positioned along a second direction horizontally. A bump is included in each of the first electrode and the second electrode and a conductive layer is disposed on a surface of the bump.

Abstract: A multi-domain vertical alignment liquid crystal display (MVA LCD) has a plurality of pixel electrodes for defining a plurality of pixel units. The pixel units are disposed in matrix arrangement, and each of them has a first electrode, a second electrode, and a third electrode. When a voltage is applied to said pixel electrode, the first electrode and the common electrode have a higher absolute voltage difference than the second electrode and the common electrode. The third electrode and the common electrode have the lowest absolute voltage difference.