Patents by Inventor Shih-Tsung Chen
Shih-Tsung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240073555Abstract: The present disclosure discloses an image processing apparatus having lens color-shading correction mechanism. A first and a second calibration circuits perform lens color-shading correction on an input image according to a first and a second calibration parameters to generate a first and a second calibrated images. A first and a second statistic circuits perform statistic on the first and the second calibrated images to generate a first and a second statistic results.Type: ApplicationFiled: July 20, 2023Publication date: February 29, 2024Inventors: SHENG-KAI CHEN, HUI-CHUN LIEN, WEN-TSUNG HUANG, SHIH-HSIANG YEN, SZU-PO HUANG
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Patent number: 11914436Abstract: An example system can include a noise sensor communicatively coupled to a controller of a computing device to dynamically determine a sound pressure level (SPL) of an environment in which the computing device is present. The computing device can include a cooling fan and the controller comprising a processor in communication with a memory resource including instructions executable to dynamically determine a threshold speed of the cooling fan based on the determined SPL of the environment set a speed of the cooling fan based on the determined threshold speed.Type: GrantFiled: September 4, 2019Date of Patent: February 27, 2024Assignee: Hewlett-Packard Development Company, L.P.Inventors: Hung-Wen Chang, Ai-Tsung Li, Shih-Han Chen
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Patent number: 11875973Abstract: Methods for preparing a void-free protective coating are disclosed herein. The void-free protective coating is used on a dielectric window having a central hole, which is used in a plasma treatment tool. A first protective coating layer is applied to the window, leaving an uncoated annular retreat area around the central hole. The first protective coating layer is polished to produce a flat surface and fill in any voids on the window. A second protective coating layer is then applied upon the flat surface of the first protective coating layer to obtain the void-free coating. This increases process uptime and service lifetime of the dielectric window and the plasma treatment tool.Type: GrantFiled: February 8, 2022Date of Patent: January 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Tsung Chen, Tsung-Cheng Ho, Chien-Yu Wang, Yen-Shih Wang, Jiun-Rong Pai, Yeh-Chieh Wang
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Publication number: 20230367339Abstract: Methods for preparing a void-free protective coating are disclosed herein. The void-free protective coating is used on a dielectric window having a central hole, which is used in a plasma treatment tool. A first protective coating layer is applied to the window, leaving an uncoated annular retreat area around the central hole. The first protective coating layer is polished to produce a flat surface and fill in any voids on the window. A second protective coating layer is then applied upon the flat surface of the first protective coating layer to obtain the void-free coating. This increases process uptime and service lifetime of the dielectric window and the plasma treatment tool.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Shih-Tsung Chen, Yeh-Chieh Wang, Yen-Shih Wang, Chien-Yu Wang, Jiun-Rng Pai, Tsung-Cheng Ho
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Publication number: 20230182181Abstract: This invention provides a method and a system for cleaning a container for storing wafers or masks. A contained with lid is washed directly after the container is loaded with lid opened in the cleaning system. Gas exchange rate in the washing station can be increased such that particles or AMC inside the container or attached to the lid can be carried out more easily. Then, contamination-free gas is purged to the container as well as lid in a high temperature environment. A vacuum station can be optionally adapted between the washing station and the contamination-free gas purging station to enhance the cleanliness of the container.Type: ApplicationFiled: March 9, 2022Publication date: June 15, 2023Inventors: Yi-Chuan PENG, Ko-Hsi CHAN, Shih Tsung CHEN
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Patent number: 11650576Abstract: A server for knowledge recommendation for defect review. The server includes a processor electronically coupled to an electronic storage device storing a plurality of knowledge files related to wafer defects. The processor is configured to execute a set of instruction to cause the server to: receive a request for knowledge recommendation for inspecting an inspection image from a defect classification server; search for a knowledge file in the electronic storage device that matches the inspection image; and transmit the search result to the defect classification server.Type: GrantFiled: January 15, 2018Date of Patent: May 16, 2023Assignee: ASML Netherlands B.V.Inventors: Wei Fang, Cho Huak Teh, Robeter Jian, Yi-Ying Wang, Shih-Tsung Chen, Jian-Min Liao, Chuan Li, Zhaohui Guo, Pang-Hsuan Huang, Shao-Wei Lai, Shih-Tsung Hsu
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Publication number: 20230110291Abstract: A grounding cap module includes a main body, a frame portion, and a cap portion. The main body includes a first opening penetrating the main body and a grounding portion disposed on a periphery of the main body and configured to be electrically grounded. The frame portion is disposed on the main body and includes a second opening aligned with the first opening. The cap portion is disposed on the frame portion and covers the second opening, wherein the first opening, the second opening and the cap portion define a receiving cavity. A gas injection device and an etching apparatus using the same are also provided.Type: ApplicationFiled: December 13, 2022Publication date: April 13, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Shi Liu, Shih-Tsung Chen
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Publication number: 20230025296Abstract: Methods for preparing a void-free protective coating are disclosed herein. The void-free protective coating is used on a dielectric window having a central hole, which is used in a plasma treatment tool. A first protective coating layer is applied to the window, leaving an uncoated annular retreat area around the central hole. The first protective coating layer is polished to produce a flat surface and fill in any voids on the window. A second protective coating layer is then applied upon the flat surface of the first protective coating layer to obtain the void-free coating. This increases process uptime and service lifetime of the dielectric window and the plasma treatment tool.Type: ApplicationFiled: February 8, 2022Publication date: January 26, 2023Inventors: Shih-Tsung Chen, Tsung-Cheng Ho, Chien-Yu Wang, Yen-Shih Wang, Jiun-Rong Pai, Yeh-Chieh Wang
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Patent number: 11551911Abstract: A grounding cap module includes a main body, a frame portion, and a cap portion. The main body includes a first opening penetrating the main body and a grounding portion disposed on a periphery of the main body and configured to be electrically grounded. The frame portion is disposed on the main body and includes a second opening aligned with the first opening. The cap portion is disposed on the frame portion and covers the second opening, wherein the first opening, the second opening and the cap portion define a receiving cavity. A gas injection device and an etching apparatus using the same are also provided.Type: GrantFiled: September 9, 2020Date of Patent: January 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Shi Liu, Shih-Tsung Chen
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Publication number: 20220359164Abstract: A cantilever for gas flow direction control configured to support an electrode housing bowl in an associated etch process chamber. The cantilever may have a cross-section that is circular, elliptical, or airfoil shaped. The shape of the cantilever induces the flow of gas and etch products within the chamber around the cantilever, reducing turbulence around the edge of a wafer.Type: ApplicationFiled: August 18, 2021Publication date: November 10, 2022Inventors: Chien-Liang Chen, Chien-Yu Wang, Wei-Da Chen, Yu-Ning Cheng, Shih-tsung Chen, Yung-Yao Lee
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Publication number: 20220351948Abstract: An apparatus includes a chamber, a pedestal configured to receive and support a semiconductor wafer in the chamber, and an edge ring disposed over the pedestal. The edge ring includes a first portion having a first top surface, a second portion coupled to the first portion and having a second top surface lower than the first top surface, and a recess defined in the first portion. The second top surface is under the semiconductor wafer. The recess has a depth, and a distance between the pedestal and an inner surface of the recess is substantially equal to the depth of the recess.Type: ApplicationFiled: July 12, 2022Publication date: November 3, 2022Inventors: HUNG-BIN LIN, LI-CHAO YIN, SHIH-TSUNG CHEN, YU-LUNG YANG, YING CHIEH WANG, BING KAI HUANG, SU-YU YEH
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Patent number: 11416979Abstract: A defect displaying method is provided in the disclosure. The method comprises acquiring defect group information from an image of a wafer, wherein the defect group information includes a set of correlations between a plurality of defects identified from the image and one or more corresponding assigned defect types and displaying at least some of the plurality of defects according to their corresponding assigned defect types.Type: GrantFiled: January 18, 2018Date of Patent: August 16, 2022Assignee: ASML Netherlands B.V.Inventors: Wei Fang, Cho Huak Teh, Ju Hao Chien, Yi-Ying Wang, Shih-Tsung Chen, Jian-Min Liao, Chuan Li, Zhaohui Guo, Pang-Hsuan Huang, Shao-Wei Lai, Shih-Tsung Hsu
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Publication number: 20210249232Abstract: An apparatus includes a chamber, a pedestal configured to receive and support a semiconductor wafer in the chamber, and an edge ring disposed over the pedestal. The edge ring includes a first portion having a first top surface, a second portion coupled to the first portion and having a second top surface lower than the first top surface, and a recess defined in the first portion. The second top surface is under the semiconductor wafer. The recess has a depth, and a distance between the pedestal and an inner surface of the recess is substantially equal to the depth of the recess.Type: ApplicationFiled: February 10, 2020Publication date: August 12, 2021Inventors: HUNG-BIN LIN, LI-CHAO YIN, SHIH-TSUNG CHEN, YU-LUNG YANG, YING CHIEH WANG, BING KAI HUANG, SU-YU YEH
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Publication number: 20200402763Abstract: A grounding cap module includes a main body, a frame portion, and a cap portion. The main body includes a first opening penetrating the main body and a grounding portion disposed on a periphery of the main body and configured to be electrically grounded. The frame portion is disposed on the main body and includes a second opening aligned with the first opening. The cap portion is disposed on the frame portion and covers the second opening, wherein the first opening, the second opening and the cap portion define a receiving cavity. A gas injection device and an etching apparatus using the same are also provided.Type: ApplicationFiled: September 9, 2020Publication date: December 24, 2020Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Shi Liu, Shih-Tsung Chen
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Patent number: 10818479Abstract: A grounding cap module includes a main body, a frame portion, and a cap portion. The main body includes a first opening penetrating the main body and a grounding portion disposed on a periphery of the main body and configured to be electrically grounded. The frame portion is disposed on the main body and includes a second opening aligned with the first opening. The cap portion is disposed on the frame portion and covers the second opening, wherein the first opening, the second opening and the cap portion define a receiving cavity. A gas injection device and an etching apparatus using the same are also provided.Type: GrantFiled: January 19, 2018Date of Patent: October 27, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, Ltd.Inventors: Li-Shi Liu, Shih-Tsung Chen
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Publication number: 20190370950Abstract: A defect displaying method is provided in the disclosure. The method comprises acquiring defect group information from an image of a wafer, wherein the defect group information includes a set of correlations between a plurality of defects identified from the image and one or more corresponding assigned defect types and displaying at least some of the plurality of defects according to their corresponding assigned defect types.Type: ApplicationFiled: January 18, 2018Publication date: December 5, 2019Inventors: Wei FANG, Cho Huak TEH, Ju Hao CHIEN, Yi-Ying WANG, Shih-Tsung CHEN, Jian-Min LIAO, Chuan LI, Zhaohui GUO, Pang-Hsuan HUANG, Shao-Wei LAI, Shih-Tsung HSU
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Publication number: 20190362488Abstract: A server for knowledge recommendation for defect review. The server includes a processor electronically coupled to an electronic storage device storing a plurality of knowledge files related to wafer defects. The processor is configured to execute a set of instruction to cause the server to: receive a request for knowledge recommendation for inspecting an inspection image from a defect classification server; search for a knowledge file in the electronic storage device that matches the inspection image; and transmit the search result to the defect classification server.Type: ApplicationFiled: January 15, 2018Publication date: November 28, 2019Inventors: Wei FANG, Cho Huak TEH, Robeter JIAN, Yi-Ying WANG, Shih-Tsung CHEN, Jian-Min LIAO, Chuan LI, Zhaohui GUO, Pang-Hsuan HUANG, Shao-Wei LAI, Shih-Tsung HSU
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Publication number: 20190148111Abstract: A grounding cap module includes a main body, a frame portion, and a cap portion. The main body includes a first opening penetrating the main body and a grounding portion disposed on a periphery of the main body and configured to be electrically grounded. The frame portion is disposed on the main body and includes a second opening aligned with the first opening. The cap portion is disposed on the frame portion and covers the second opening, wherein the first opening, the second opening and the cap portion define a receiving cavity. A gas injection device and an etching apparatus using the same are also provided.Type: ApplicationFiled: January 19, 2018Publication date: May 16, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Shi Liu, Shih-Tsung Chen
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Patent number: 9251581Abstract: A method for promoting semiconductor manufacturing yield comprising the following steps and a computer readable medium encoded with a computer program implementing the method is provided. First, a processed layer is inspected to generate an inspected image with defects thereon. Next, the inspected image is aligned to an original design layout information of the processed layer. In addition, the defects are classified according to geometric features of the original design layout information of the processed layer and at least previous one layer and/or at least next one layer.Type: GrantFiled: March 28, 2011Date of Patent: February 2, 2016Assignee: HERMES MICROVISION, INC.Inventors: Shih-Tsung Chen, Wei Fang, Yu-Tsorng Fu, Futang Peng, Zhao-Li Zhang
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Patent number: D1020435Type: GrantFiled: November 8, 2021Date of Patent: April 2, 2024Assignee: BROGENT TECHNOLOGIES INC.Inventors: Shih-Kuang Chiu, Chia-Wei Yeh, Juei-Tsung Chen