Patents by Inventor Shih-Wei Li

Shih-Wei Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176335
    Abstract: A fault detection method, includes the following steps. A target sequence is received, the target sequence includes several data. A first moving average operation is performed on the target sequence to establish a first moving average sequence. A second moving average operation is performed on the target sequence to establish a second moving average sequence. A difference operation between the first moving average sequence and the second moving average sequence is performed to obtain a difference sequence, the difference sequence includes several difference values. An upper limit value is set. When one of the difference values is greater than the upper limit value, the target sequence is determines as abnormal.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Inventors: Yung-Yu Yang, Kang-Ping Li, Chih-Kuan Chang, Chung-Chih Hung, Chen-Hui Huang, Nai-Ying Lo, Shih-Wei Huang
  • Publication number: 20240145691
    Abstract: The present invention is related to a novel positive electrode active material for lithium-ion battery. The positive electrode active material is expressed by the following formula: Li1.2NixMn0.8-x-yZnyO2, wherein x and y satisfy 0<x?0.8 and 0<y?0.1. In addition, the present invention provides a method of manufacturing the positive electrode active material. The present invention further provides a lithium-ion battery which uses said positive electrode active material.
    Type: Application
    Filed: March 14, 2023
    Publication date: May 2, 2024
    Inventors: CHUAN-PU LIU, YIN-WEI CHENG, SHIH-AN WANG, BO-LIANG PENG, CHUN-HUNG CHEN, JUN-HAN HUANG, YI-CHANG LI
  • Publication number: 20230043220
    Abstract: The present invention relates to a method for preparing etelcalcetide hydrochloride (etelcalcetide HCL). A first peptide is de-protected and cleaved from a solid support by a first solution system, for obtaining a second peptide, followed by coupling an activated L-Cys-OH to the second peptide in the second solution system for forming a TFA salt of etelcalcetide that is not or hardly dissolved in the second solution system. After purification by column chromatography, the TFA salt of etelcalcetide can be converted to etelcalcetide HCL using a third solution system that excludes hydrogen chloride during a real-time monitoring salt exchange step. The present method provides a simplified process and the etelcalcetide HCL with high purity and yield, for being advantageously applied in mass production of etelcalcetide HCL.
    Type: Application
    Filed: July 18, 2022
    Publication date: February 9, 2023
    Inventors: Ya-Chun CHANG, Shih-Wei LI
  • Patent number: 10960140
    Abstract: A mini syringe includes a tubular base member, a microneedle unit including a microneedle device and a compressible pharmacy housing device and mounted in the bottom side of the base member, a plunger mounted in the base member and pressable to compress the pharmacy housing device, and an adjustment cover threaded onto the base member for controlling the moving distance of the plunger in a micro-adjustable manner.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 30, 2021
    Assignee: Yomura Technologies Inc.
    Inventors: Liang-Chuan Liu, Shih-Wei Li
  • Publication number: 20200409740
    Abstract: Systems comprising: a memory; and a hardware processor and configured to: execute a hypervisor having a first portion and a second portion, wherein the first portion of the hypervisor executes at a first exception level that allows the first portion to access data of a virtual machine in the hardware processor and the memory, and wherein the second portion of the hypervisor executes at a second exception level that prevents the second portion from accessing the data of the virtual machine in the hardware processor and the memory. Methods comprising: executing a first portion of a hypervisor at a first exception level that allows the first portion to access data of a virtual machine in a hardware processor and memory; and executing a second portion of a hypervisor at a second exception level that prevents the second portion from accessing the data in the hardware processor and the memory.
    Type: Application
    Filed: June 29, 2020
    Publication date: December 31, 2020
    Inventors: Shih-Wei Li, Xupeng Li, Ronghui Gu, Jason Nieh
  • Patent number: 10793426
    Abstract: A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a MEMS structure includes the following steps. A first substrate is provided, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon. A second substrate is provided, wherein a second dielectric layer and a thermal stability layer are formed on the second substrate. The first substrate is bonded to the second substrate, and the second substrate removed. A conductive layer is formed within the second dielectric layer and electrically connected to the interconnection structure. The thermal stability layer is located between the conductive layer and the interconnection structure. A growth temperature of a material of the thermal stability layer is higher than a growth temperature of a material of the conductive layer and a growth temperature of a material of the interconnection structure.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 6, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Sheng Hsu, Chih-Fan Hu, Chia-Wei Lee, En Chan Chen, Shih-Wei Li
  • Patent number: 10773953
    Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Meng-Jia Lin, Yung-Hsiao Lee, Weng-Yi Chen, Shih-Wei Li, Chung-Hsien Liu
  • Publication number: 20200086058
    Abstract: A mini syringe includes a tubular base member, a microneedle unit including a microneedle device and a compressible pharmacy housing device and mounted in the bottom side of the base member, a plunger mounted in the base member and pressable to compress the pharmacy housing device, and an adjustment cover threaded onto the base member for controlling the moving distance of the plunger in a micro-adjustable manner.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Inventors: LIANG-CHUAN LIU, SHIH-WEI LI
  • Patent number: 10423408
    Abstract: A computer system, method, and computer readable product are provided for identifying and isolating library code that has been obfuscated in software applications. A call graph is created for the execution of at least one module of preexisting library code within a bundle of software modules through either static analysis of the software code or dynamic analysis of the executing code, and then one or more anchor points are devised based upon the call graph that are indicative of the preexisting library code. Then a bundle of software modules can be analyzed or its execution monitored to determine if a discrete module of library code is present in the executing bundle based upon the modules' interaction with the one or more anchor points, and the discrete module of library code in the executing bundle can be identified as a module of preexisting library code.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Salman A. Baset, Shih-Wei Li, Omer Tripp, Philippe Suter
  • Patent number: 10201694
    Abstract: A medical catheter control valve includes a valve body defining a fluid channel and a single open-end hole extended across the fluid channel, and a click-on mechanism consisting of a plunger unit with a through hole and a spring member and mounted in the single open-end hole. When click the plunger unit, the plunger unit is shifted to keep the through hole in alignment with the fluid channel for allowing a fluid to pass through the fluid channel. When push back the plunger unit, the through hole is deviated from the fluid channel and the fluid channel is blocked. Thus, the medical catheter control valve can be conveniently controlled with one single hand.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: February 12, 2019
    Inventors: Liang-Chuan Liu, Shih-Wei Li
  • Publication number: 20180354783
    Abstract: A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a MEMS structure includes the following steps. A first substrate is provided, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon. A second substrate is provided, wherein a second dielectric layer and a thermal stability layer are formed on the second substrate. The first substrate is bonded to the second substrate, and the second substrate removed. A conductive layer is formed within the second dielectric layer and electrically connected to the interconnection structure. The thermal stability layer is located between the conductive layer and the interconnection structure. A growth temperature of a material of the thermal stability layer is higher than a growth temperature of a material of the conductive layer and a growth temperature of a material of the interconnection structure.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Chang-Sheng Hsu, Chih-Fan Hu, Chia-Wei Lee, En Chan Chen, Shih-Wei Li
  • Publication number: 20180339901
    Abstract: A semiconductor process including the following steps is provided. A wafer is provided. The wafer has a front side and a back side. The wafer has a semiconductor device on the front side. A protection layer is formed on the front side of the wafer. The protection layer covers the semiconductor device. A material of the protection layer includes a photoresist material. A surface hardening treatment process is performed on the protection layer. A first patterning process is performed on the back side of the wafer. The semiconductor process can effectively protect the front side of the wafer during a backside process.
    Type: Application
    Filed: July 7, 2017
    Publication date: November 29, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Guo-Chih Wei, Weng-Yi Chen, Shih-Wei Li
  • Patent number: 10087072
    Abstract: A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a MEMS structure includes the following steps. A first substrate is provided, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon. A second substrate is provided, wherein a second dielectric layer and a thermal stability layer are formed on the second substrate. The first substrate is bonded to the second substrate, and the second substrate removed. A conductive layer is formed within the second dielectric layer and electrically connected to the interconnection structure. The thermal stability layer is located between the conductive layer and the interconnection structure. A growth temperature of a material of the thermal stability layer is higher than a growth temperature of a material of the conductive layer and a growth temperature of a material of the interconnection structure.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: October 2, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Sheng Hsu, Chih-Fan Hu, Chia-Wei Lee, En Chan Chen, Shih-Wei Li
  • Publication number: 20180264253
    Abstract: A medical catheter control valve includes a valve body defining a fluid channel and a single open-end hole extended across the fluid channel, and a click-on mechanism consisting of a plunger unit with a through hole and a spring member and mounted in the single open-end hole. When click the plunger unit, the plunger unit is shifted to keep the through hole in alignment with the fluid channel for allowing a fluid to pass through the fluid channel. When push back the plunger unit, the through hole is deviated from the fluid channel and the fluid channel is blocked. Thus, the medical catheter control valve can be conveniently controlled with one single hand.
    Type: Application
    Filed: March 17, 2017
    Publication date: September 20, 2018
    Inventors: LIANG-CHUAN LIU, SHIH-WEI LI
  • Patent number: 9961450
    Abstract: A piezoresistive microphone includes a substrate, an insulating layer, and a polysilicon layer. A first pattern is disposed within the polysilicon layer. The first pattern includes numerous first opening. A second pattern is disposed within the polysilicon layer. The second pattern includes numerous second openings. The first pattern surrounds the second pattern. Each first opening and each second opening are staggered. A first resistor is disposed in the polysilicon and between the first pattern and the second pattern. The first resistor is composed of numerous first heavily doped regions and numerous first lightly doped regions. The first heavily doped regions and the first lightly doped regions are disposed in series. The first heavily doped region and the first lightly doped region are disposed alternately. A cavity is disposed in the insulating layer and the substrate.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: May 1, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Sheng Hsu, Weng-Yi Chen, En-Chan Chen, Shih-Wei Li, Guo-Chih Wei
  • Publication number: 20180027337
    Abstract: A piezoresistive microphone includes a substrate, an insulating layer, and a polysilicon layer. A first pattern is disposed within the polysilicon layer. The first pattern includes numerous first opening. A second pattern is disposed within the polysilicon layer. The second pattern includes numerous second openings. The first pattern surrounds the second pattern. Each first opening and each second opening are staggered. A first resistor is disposed in the polysilicon and between the first pattern and the second pattern. The first resistor is composed of numerous first heavily doped regions and numerous first lightly doped regions. The first heavily doped regions and the first lightly doped regions are disposed in series. The first heavily doped region and the first lightly doped region are disposed alternately. A cavity is disposed in the insulating layer and the substrate.
    Type: Application
    Filed: August 25, 2016
    Publication date: January 25, 2018
    Inventors: Chang-Sheng Hsu, Weng-Yi Chen, En-Chan Chen, Shih-Wei Li, Guo-Chih Wei
  • Publication number: 20170362081
    Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.
    Type: Application
    Filed: September 7, 2017
    Publication date: December 21, 2017
    Inventors: Meng-Jia Lin, Yung-Hsiao Lee, Weng-Yi Chen, Shih-Wei Li, Chung-Hsien Liu
  • Publication number: 20170351597
    Abstract: A computer system, method, and computer readable product are provided for identifying and isolating library code that has been obfuscated in software applications. A call graph is created for the execution of at least one module of preexisting library code within a bundle of software modules through either static analysis of the software code or dynamic analysis of the executing code, and then one or more anchor points are devised based upon the call graph that are indicative of the preexisting library code. Then a bundle of software modules can be analyzed or its execution monitored to determine if a discrete module of library code is present in the executing bundle based upon the modules' interaction with the one or more anchor points, and the discrete module of library code in the executing bundle can be identified as a module of preexisting library code.
    Type: Application
    Filed: June 2, 2016
    Publication date: December 7, 2017
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Salman A. Baset, Shih-Wei Li, Omer Tripp, Philippe Suter
  • Publication number: 20170320727
    Abstract: A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a MEMS structure includes the following steps. A first substrate is provided, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon. A second substrate is provided, wherein a second dielectric layer and a thermal stability layer are formed on the second substrate. The first substrate is bonded to the second substrate, and the second substrate removed. A conductive layer is formed within the second dielectric layer and electrically connected to the interconnection structure. The thermal stability layer is located between the conductive layer and the interconnection structure. A growth temperature of a material of the thermal stability layer is higher than a growth temperature of a material of the conductive layer and a growth temperature of a material of the interconnection structure.
    Type: Application
    Filed: May 4, 2016
    Publication date: November 9, 2017
    Inventors: Chang-Sheng Hsu, Chih-Fan Hu, Chia-Wei Lee, En Chan Chen, Shih-Wei Li
  • Patent number: 9790088
    Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: October 17, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Meng-Jia Lin, Yung-Hsiao Lee, Weng-Yi Chen, Shih-Wei Li, Chung-Hsien Liu