Patents by Inventor Shih-Wei Liang
Shih-Wei Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10079200Abstract: A method of manufacturing a packaging device may include: forming a plurality of through-substrate vias (TSVs) in a substrate, wherein each of the plurality of TSVs has a protruding portion extending away from a major surface of the substrate. A seed layer may be forming over the protruding portions of the plurality of TSVs, and a conductive ball may be coupled to the seed layer and the protruding portion of each of the plurality of TSVs. The seed layer and the protruding portion of each of the plurality of TSVs may extend into an interior region of the conductive ball.Type: GrantFiled: May 16, 2017Date of Patent: September 18, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Shih-Wei Liang, Kai-Chiang Wu, Ming-Che Ho, Yi-Wen Wu
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Patent number: 10062654Abstract: A semiconductor structure has an integrated circuit component, a conductive contact pad, a seal ring structure, a conductive via, a ring barrier, and a mold material. The conductive contact pad is disposed on and electrically connected with the integrated circuit component. The seal ring structure is disposed on the integrated circuit component and surrounding the conductive contact pad. The conductive via is disposed on and electrically connected with the conductive contact pad. The ring barrier is disposed on the seal ring structure. The ring barrier surrounds the conductive via. The mold material covers side surfaces of the integrated circuit component. A semiconductor manufacturing process is also provided.Type: GrantFiled: July 20, 2016Date of Patent: August 28, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chia Lai, Chen-Hua Yu, Chang-Pin Huang, Chung-Shi Liu, Hsien-Ming Tu, Hung-Yi Kuo, Hao-Yi Tsai, Shih-Wei Liang, Ren-Xuan Liu
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Publication number: 20180240723Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.Type: ApplicationFiled: April 20, 2018Publication date: August 23, 2018Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
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Publication number: 20180233472Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.Type: ApplicationFiled: April 12, 2018Publication date: August 16, 2018Inventors: CHAO-WEN SHIH, KAI-CHIANG WU, CHING-FENG YANG, MING-KAI LIU, SHIH-WEI LIANG, YEN-PING WANG
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Patent number: 10049990Abstract: An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.Type: GrantFiled: March 7, 2014Date of Patent: August 14, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu
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Patent number: 10037959Abstract: A semiconductor structure includes a conductive bump, and a ferromagnetic member extended within the conductive bump, wherein a center of the conductive bump is disposed on a central axis of the ferromagnetic member.Type: GrantFiled: September 29, 2016Date of Patent: July 31, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Chun Miao, Shih-Wei Liang, Yen-Ping Wang, Kai-Chiang Wu, Ming-Kai Liu
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Publication number: 20180211935Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad.Type: ApplicationFiled: March 20, 2018Publication date: July 26, 2018Inventors: MING-KAI LIU, CHUN-LIN LU, KAI-CHIANG WU, SHIH-WEI LIANG, CHING-FENG YANG, YEN-PING WANG, CHIA-CHUN MIAO
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Patent number: 9978704Abstract: A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally, the semiconductor device includes a post passivation interconnect (PPI) line over the metal pad, where the PPI line is in contact with the metal pad. Furthermore, the semiconductor device includes an under-bump-metallurgy (UBM) layer over the PPI line. Moreover, the semiconductor device includes a plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern.Type: GrantFiled: September 2, 2016Date of Patent: May 22, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Ying-Ju Chen, Shih-Wei Liang
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Patent number: 9966321Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.Type: GrantFiled: October 26, 2016Date of Patent: May 8, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
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Patent number: 9953942Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.Type: GrantFiled: November 10, 2016Date of Patent: April 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chao-Wen Shih, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Shih-Wei Liang, Yen-Ping Wang
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Patent number: 9953966Abstract: A semiconductor device having a semiconductor substrate is provided. The semiconductor substrate includes an integrated circuit, which includes multi-layer structured metallization and inter-metal dielectric. The integrated circuit is below a passivation, which is over a metal structure. The metal structure includes a metal pad and an under bumper metallurgy, which is over and aligned with the metal pad. The metal pad is electrically connected to the integrated circuit, and the under bumper metallurgy is configured to electrically connect to a conductive component of another semiconductor device. The integrated circuit further includes a conductive trace, which is below and aligned with the metal structure. The conductive trace is connected to a power source such that an electromagnetic field is generated at the conductive trace when an electric current from the power source passes through the conductive trace.Type: GrantFiled: January 14, 2016Date of Patent: April 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu, Yen-Ping Wang
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Patent number: 9943239Abstract: An optical sensing system is disclosed. The optical sensing system includes a printed circuit board (PCB), a supporter and an optical sensor. The PCB includes a top surface, a bottom surface and a through cavity, wherein the through cavity extends downwardly from the top surface to the bottom surface. The supporter has a top surface and a bottom surface. The optical sensor is bonded and coupled to the top surface of the supporter, wherein the optical sensor includes a primary optic structure. Wherein the supporter is flipped over and bonded to the PCB with the top surface facing the through cavity, so that the optical sensor is coupled to the PCB and at least partially extends to the through cavity. Associated electronic devices are also disclosed.Type: GrantFiled: March 7, 2016Date of Patent: April 17, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hung-Yi Kuo, Hao-Yi Tsai, Hsien-Ming Tu, Shih-Wei Liang, Chang-Pin Huang, Chih-Hua Chen, Yu-Feng Chen, Chen-Hua Yu
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Patent number: 9941240Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad. A method of forming a surface mounting component or a chip scale package assembly wherein the component or assembly has at least two different types of solder bumps.Type: GrantFiled: July 3, 2013Date of Patent: April 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Kai Liu, Chun-Lin Lu, Kai-Chiang Wu, Shih-Wei Liang, Ching-Feng Yang, Yen-Ping Wang, Chia-Chun Miao
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Publication number: 20180061798Abstract: A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface.Type: ApplicationFiled: October 30, 2017Publication date: March 1, 2018Inventors: CHUN-LIN LU, KAI-CHIANG WU, MING-KAI LIU, YEN-PING WANG, SHIH-WEI LIANG, CHING-FENG YANG, CHIA-CHUN MIAO, HAO-YI TSAI
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Publication number: 20180033725Abstract: A semiconductor device includes a first molding layer; a second molding layer formed over the first molding layer; a first conductive coil including a first portion continuously formed in the first molding layer and a second portion continuously formed in the second molding layer, wherein the first and the second portions are laterally displaced from each other; and a second conductive coil formed in the second molding layer, wherein the second conductive coil is interweaved with the second portion of the first conductive coil in the second molding layer.Type: ApplicationFiled: July 28, 2016Publication date: February 1, 2018Inventors: Shih-Wei LIANG, Hung-Yi KUO, Hao-Yi TSAI, Ming-Hung TSENG, Hsien-Ming TU
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Publication number: 20180033750Abstract: A method of manufacturing a semiconductor structure include: providing a die including a die pad disposed over the die; disposing a conductive member over the die pad of the die; forming a molding surrounding the die and the conductive member; disposing a dielectric layer over the molding, the die and the conductive member; and forming an interconnect structure including a land portion and a plurality of via portions. The land portion is disposed over the dielectric layer, the plurality of via portions are disposed over the conductive member and protruded from the land portion to the conductive member through the dielectric layer, and each of the plurality of via portions at least partially contacts with the conductive member.Type: ApplicationFiled: October 6, 2017Publication date: February 1, 2018Inventors: CHANG-PIN HUANG, HSIEN-MING TU, CHING-JUNG YANG, SHIH-WEI LIANG, HUNG-YI KUO, YU-CHIA LAI, HAO-YI TSAI, CHUNG-SHI LIU, CHEN-HUA YU
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Publication number: 20180025997Abstract: A semiconductor structure has an integrated circuit component, a conductive contact pad, a seal ring structure, a conductive via, a ring barrier, and a mold material. The conductive contact pad is disposed on and electrically connected with the integrated circuit component. The seal ring structure is disposed on the integrated circuit component and surrounding the conductive contact pad. The conductive via is disposed on and electrically connected with the conductive contact pad. The ring barrier is disposed on the seal ring structure. The ring barrier surrounds the conductive via. The mold material covers side surfaces of the integrated circuit component. A semiconductor manufacturing process is also provided.Type: ApplicationFiled: July 20, 2016Publication date: January 25, 2018Inventors: Yu-Chia Lai, Chen-Hua Yu, Chang-Pin Huang, Chung-Shi Liu, Hsien-Ming Tu, Hung-Yi Kuo, Hao-Yi Tsai, Shih-Wei Liang, Ren-Xuan Liu
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Publication number: 20170372999Abstract: A conductive terminal on an integrated circuit is provided. The conductive terminal includes a conductive pad, a dielectric layer, and a conductive via. The conductive pad is disposed on and electrically to the integrated circuit. The dielectric layer covers the integrated circuit and the conductive pad, the dielectric layer includes a plurality of contact openings arranged in array, and the conductive pad is partially exposed by the contact openings. The conductive via is disposed on the dielectric layer and electrically connected to the conductive pad through the contact openings. The conductive via includes a plurality of convex portions arranged in array. The convex portions are distributed on a top surface of the conductive via, and the convex portions are corresponding to the contact openings.Type: ApplicationFiled: September 25, 2016Publication date: December 28, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chia Lai, Chen-Hua Yu, Chang-Pin Huang, Chung-Shi Liu, Hsien-Ming Tu, Hung-Yi Kuo, Hao-Yi Tsai, Shih-Wei Liang, Ren-Xuan Liu
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Patent number: 9852985Abstract: A conductive terminal on an integrated circuit is provided. The conductive terminal includes a conductive pad, a dielectric layer, and a conductive via. The conductive pad is disposed on and electrically to the integrated circuit. The dielectric layer covers the integrated circuit and the conductive pad, the dielectric layer includes a plurality of contact openings arranged in array, and the conductive pad is partially exposed by the contact openings. The conductive via is disposed on the dielectric layer and electrically connected to the conductive pad through the contact openings. The conductive via includes a plurality of convex portions arranged in array. The convex portions are distributed on a top surface of the conductive via, and the convex portions are corresponding to the contact openings.Type: GrantFiled: September 25, 2016Date of Patent: December 26, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chia Lai, Chen-Hua Yu, Chang-Pin Huang, Chung-Shi Liu, Hsien-Ming Tu, Hung-Yi Kuo, Hao-Yi Tsai, Shih-Wei Liang, Ren-Xuan Liu
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Patent number: 9806045Abstract: A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a height of the post to a longest length of the UBM pad is between about 0.25 and about 0.7. A method of manufacturing a semiconductor device includes providing a carrier, disposing a UBM pad on the carrier and forming a post on the UBM pad.Type: GrantFiled: August 29, 2013Date of Patent: October 31, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hao-Yi Tsai