Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of three oxide layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out while keeping the substrate unbiased to form an oxide layer over the lines and in the gap. A second HDPCVD step in which the substrate is biased deposits a second oxide layer over the first oxide layer. During the second HDPCVD step some etching occurs and a portion of the first oxide layer is removed. A third HDPCVD step is carried out at a greater etch and sputtering rate than the second step to complete filling of the gap with dielectric material. The first oxide layer acts to protect the underlying structures from etching damage during the third step. Gaps between wiring lines can be filled with dielectric material without forming voids, even for high aspect ratio gaps.

Abstract: A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure in an integrated circuit, which can prevent the occurrence of microscratches in the oxide plugs of the STI structure, thus further preventing the occurrence of a bridging effect and short-circuits between the circuit components that are intended to be electrically isolated by the STI structure. This method is characterized by the use of a laser annealing process to remove the microscratches that formed on the top surface of the oxide plugs during the chemical-mechanical polishing (CMP) process used to remove the upper part of the oxide layer to form the oxide plugs This method can therefore prevent the occurrence of a bridging effect and short-circuits due to the forming of the microscratches that would otherwise occur in the prior art.

Abstract: An SRAM cell having improved stability includes pass transistors having gate electrodes which are shaped by oxidation so that the lower edges of the gate electrodes are raised away from the substrate surface. Because the gate electrodes of the load and pull-down transistors are masked during the oxidation process, the gate electrodes of the load and pull-down transistors have the conventional rectangular shape. The modified shape of the gate electrodes of the pass transistors decreases the current flowing through the pass transistors relative to that which flows through the pull-down transistors, reducing the likelihood that data can inadvertently be lost from the SRAM cell.

Abstract: An integrated circuit device having both an array of logic circuits and embedded DRAM circuits is provided using a process that avoids some of the most significant processing challenges for embedded DRAM integration. Transfer FETs and wiring lines are provided for the embedded DRAM circuits and FETs are provided for the logic portions of the device. A thin, conformal oxide layer is provided over the surface of the device to cover the transfer FETs and the logic FETs to protect portions of the device during formation of the charge storage capacitors. A mask is provided having openings over the appropriate source/drain regions of the transfer FETs and the oxide layer is etched. A planar or substantially planar lower capacitor electrode is defined by providing and patterning a first layer of doped polysilicon over the thin protective oxide layer in contact with the desired source/drain regions of the transfer FETs.

Abstract: Different thicknesses of gate oxide can be formed on a single chip in a single oxidation process by selectively implanting nitrogen into the surface of the chip in a pattern corresponding to the desired differences in gate oxide thickness. Implanting nitrogen to a silicon substrate reduces the rate at which oxide grows on the surface. Thus, by implanting different dosages of nitrogen into the surface of the substrate, thicker or thinner oxide layers can be provided. A processing chip with embedded DRAM can then be formed where the logic circuitry has a thin gate oxide and the DRAM circuitry has a thick gate oxide by implanting the higher dosage of nitrogen into the region of the chip where the logic circuits are to be formed. Different gate oxide thicknesses are then provided by exposing both the logic circuitry and the embedded DRAM section to a single thermal oxidation process.

Abstract: The invention provides a novel method, in which self-aligned, borderless contacts and local interconnections of semiconductor devices are manufactured in an integral process. The method is compatible with the LOGIC self-aligned titanium silicide (SALICIDE) and N+/P+ poly dual gate process modules. That is, this invention provides a self-aligned local-interconnect and contact (SALIC) method for a logic technology to forming the self-aligned, borderless contacts, and local interconnects (LI) simultaneously.

Abstract: A method of planarizing an inter-layer dielectric layer includes using a high density plasma chemical vapor deposition method to deposit an undoped dielectric, which increases the polishing efficiency in a subsequent chemical-mechanical polishing operation, and eliminates the need for a high temperature densifying treatment for planarization. A chemical-mechanical polishing operation is used to planarize the inter-layer dielectric.

Abstract: An SRAM cell having improved soft error immunity connects each of the storage nodes of the SRAM cell to an overlying electrode having a textured surface which is separated from a constant potential plate electrode by a dielectric layer. The textured surface of the overlying electrode may be created by forming hemispherical-grained silicon on its surface, or by forming a fin structure on its surface. The textured surface of the overlying electrode provides increased capacitance between the overlying electrode and the constant potential plate electrode, thereby increasing the capacitance of the storage node.

Abstract: A method of forming self-aligned silicide devices which includes providing a silicon substrate having shallow trench isolation regions for defining a device area formed therein; then, forming sequentially a gate oxide layer, a polysilicon layer, a first titanium nitride layer, a titanium silicide layer, a second titanium nitride layer and a silicon nitride layer over the substrate. After a gate electrode is etched out from the above layers, a titanium layer is deposited over the device, and then a self-aligned titanium silicide layer is formed using a heating process.

Abstract: A high capacitance charge storage capacitor for a DRAM has a lower electrode in contact with one source/drain region of a transfer FET. The lower capacitor electrode includes a first layer of polysilicon deposited over part of the transfer FET and in contact with the source/drain region of the transfer FET. An oxide layer is deposited over the first polysilicon layer and then a sparse layer of hemispherical grained polysilicon is deposited on the surface of the oxide layer. The sparse layer of hemispherical grained polysilicon has grains on the order of approximately 100 nanometers across that are separated on the average by approximately 100 nanometers. The layer of oxide is etched using the sparse grains of hemispherical grained polysilicon as a mask, with the etch process stopping on the surface of the first layer of polysilicon.

Abstract: The channel doping profile of a PMOS field effect transistor consists of a shallow distribution of a P-type dopant as a threshold adjust implant, a deeper distribution of an N-type dopant as an buried channel stop implant and a still deeper implantation of an N-type dopant as an antipunchthrough implant. A junction is formed between the P-type threshold adjust implant and the N-type buried channel stop implant at a relatively shallow depth so that the depth of the buried channel region is limited by the buried channel stop implant, reducing the short channel effect. The channel doping profile is formed so that diffusion of impurities from the channel region to the gate oxide is prevented. The buried channel stop implant is made first through a sacrificial oxide layer. The sacrificial oxide is etched and a gate oxide layer and a thin film of polysilicon are deposited on the surface of the gate oxide.

Abstract: A silicon on insulator (SOI) DRAM has a layer of buried oxide covered by a thin layer of crystalline silicon on the surface of a bulk silicon substrate. Field oxide regions are formed extending through the thin crystalline silicon surface layer and into contact with the buried oxide layer. Gate oxide layers, gate electrodes and source/drain regions for the transfer FETs of the DRAM are formed in and on the thin crystalline silicon surface layer in the active regions between the field oxide regions. A trench is opened through one of the source/drain regions of each of the transfer FETs. A layer of doped polysilicon is provided to line the trenches and is patterned to form at least a part of the bottom electrodes of the charge storage capacitors for the DRAM. The bottom electrodes are covered with a thin dielectric layer and an upper electrode of doped polysilicon is provided. Preferably, the trench for the bottom capacitor electrode extends through the buried oxide layer and may extend into the bulk silicon.

Abstract: A dual damascene process forms a two level metal interconnect structure by first providing a interlayer oxide over a device structure and covering the interlevel oxide layer with an etch stop layer. The etch stop layer is patterned to form openings corresponding to the pattern of the interconnects that are to be formed in the first level of the two level interconnect structure. After the etch stop layer is patterned, an intermetal oxide layer is provided over the etch stop layer. Because the etch stop layer is relatively thin, the topography formed on the surface of the intermetal oxide layer is relatively small. A photoresist mask is then provided over the intermetal oxide layer with openings in the mask exposing portions of the intermetal oxide layer in the pattern of the wiring lines to be provided in the second level of the interconnect structure.

Abstract: Pass transistors are formed on the active device regions of a substrate and a layer of silicon oxide is deposited over the transistors and the surface of the layer of silicon oxide is planarized. A thin layer of silicon nitride is deposited on the oxide layer and then vias are opened through the silicon nitride and silicon oxide layers to expose one of the source/drain regions of each of the pass transistors in the memory array. A layer of polysilicon is deposited so as to extend through the vias, forming polysilicon vertical interconnects in contact with the source/drain regions of the pass transistors and then the layer of polysilicon is patterned to form capacitor bottom plates, with each of the capacitor bottom plates connected to a corresponding source/drain region. A second layer of silicon oxide is deposited to cover the capacitor bottom plates and photolithography is performed to provide a plurality of openings through the second silicon oxide layer to each of the capacitor bottom plates.

Abstract: A method of making a self-aligned silicide component having parasitic spacers formed on the sides of an upper surface of the component isolating regions, the bottom sides of the spacers and the exposed sides of the gate regions, which increases a distance from a metal silicide layer at a corner of an active region neighboring the component isolating region to the source/drain junction, to prevent undesired current leakages. The formation of parasitic spacers increases a distance from the metal silicide layer lying above the gate surface to the metal silicide layer lying above the source/drain surface so that an ability to withstand electrostatic damages is enhanced.

Abstract: Hemispherical-grained silicon (HSG-Si) is grown on polysilicon by plasma deposition. A wider range of substrate deposition temperatures can be used in the plasma deposition of HSG-Si than can be maintained in the low pressure chemical vapor deposition (LPCVD) of HSG-Si. The plasma deposition of HSG-Si can be performed in an electron cyclotron resonance chemical vapor deposition (ECR-CVD) system at input power levels ranging from 100-1500 W, at total pressures between 5-60 mTorr, and at substrate temperatures ranging from 200.degree.-500.degree. C. A mixture of silane and hydrogen gases at a dilution ratio of silane within the silane and hydrogen gas mixture H.sub.2 /(SiH.sub.4 +H.sub.2) between about 70-99% may be used in the ECR-CVD system. The polysilicon surface is cleaned of native oxides prior to plasma deposition of HSG-Si.

Abstract: A semiconductor device with an electrostatic discharge (ESD) protection transistor is devised, wherein the ESD protection transistor has halo regions of an opposite conductivity type from the source and drain regions adjacent thereto. In one embodiment, the ESD protection transistor is a thick field oxide (TFO) transistor. In some cases, the halo regions may be provided with an ion implant step without the use of an extra mask. The halo regions permit the ESD protection transistor to have its breakdown voltage adjusted so that it turns on before the device it is protecting is affected by an ESD event. The use of halo regions avoids the increase in device area and adverse effects to the AC performance of the circuit being protected that are disadvantages of prior approaches.

Abstract: A semiconductor device with an electrostatic discharge (ESD) protection transistor is devised, wherein the ESD protection transistor has halo regions of an opposite conductivity type from the source and drain regions adjacent thereto. In one embodiment, the ESD protection transistor is a thick field oxide (TFO) transistor. In some cases, the halo regions may be provided with an ion implant step without the use of an extra mask. The halo regions permit the ESD protection transistor to have its breakdown voltage adjusted so that it turns on before the device it is protecting is affected by an ESD event. The use of halo regions avoids the increase in device area and adverse effects to the AC performance of the circuit being protected that are disadvantages of prior approaches.

Abstract: A thin film silicon on insulator circuit with a low voltage triggered, surface silicon controlled rectifier (30) for electrostatic damage protection and method is provided. A surface silicon controller rectifier (30) is formed in a thin device layer (130), overlying a buried insulation layer (110) and electrically coupled to a low voltage trigger apparatus (36). In one embodiment, a zener diode is employed as the low voltage trigger apparatus (36), and in another embodiment low voltage trigger apparatus (36) is an n-channel MOSFET.

Abstract: Interconnects (22 and 32) are formed within an insulating base material of a first substrate. Trenches (54) and portions of an insulating layer (52) are formed within a second substrate (50). The two substrates are bonded by fusion. The second substrate is polished back to form semiconductor islands (81-83) over the first substrate. Active regions of transistors are formed within the islands (81-83). Conductive plugs (131-134) are made between portions of the active regions and interconnects (22, 32, and 141) that underlie or overlie the semiconductor islands (81-83). Embodiments of the present invention allow higher component density, better thickness control for SOI regions, and lower leakage current compared to SOI layers that use LOCOS-type field isolation.