Abstract: A rearview mirror with display function includes a display structure layer, a rearview mirror structure layer, a plastic frame and an electrochromic material. The display structure layer includes a first transparent substrate, a display body layer and a transflective layer on opposite sides of the first transparent substrate. The rearview mirror structure layer is disposed on one side of the display structure layer, and includes a second transparent substrate, a ring-shaped shielding layer, a touch sensing layer, an insulating substrate, and a transparent electrode layer. The ring-shaped shielding layer is disposed around a third surface of the second transparent substrate, and the touch sensing layer covers the third surface and the ring-shaped shielding layer. The ring-shaped shielding layer is electrically insulated from the touch sensing layer. The plastic frame, the transflective layer and the transparent electrode layer define an accommodating space.

Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.

Abstract: A semiconductor device and method for fabricating a semiconductor device includes etch selectivity tuning to enlarge epitaxy process windows. Through modification of etching processes and careful selection of materials, improvements in semiconductor device yield and performance can be delivered. Etch selectivity is controlled by using dilute gas, using assistive etch chemicals, controlling a magnitude of bias power used in the etching process, and controlling an amount of passivation gas used in the etching process, among other approaches. A recess is formed in a dummy fin in a region of the semiconductor where epitaxial growth occurs to further enlarge the epitaxy process window.

Abstract: An electrochromic mirror module including a light-transmissive substrate, an opaque touch sensing layer and an electrochromic device is provided. The light-transmissive substrate has a visible surface and a back surface disposed opposite to the visible surface. The opaque touch sensing layer and the electrochromic layer are disposed on the back surface. Distribution areas of the opaque touch sensing layer and the electrochromic layer are different on the back surface. An electrochromic mirror module including reflective layer and electrochromic device is also provided.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction. The gate structure includes a first portion and a second portion separated by the gate isolation structure and the dielectric fin. The first portion of the gate structure presents a first beak profile and the second portion of the gate structure presents a second beak profile. The first and second beak profiles point toward each other.

Abstract: A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a fin layer. Dummy gates are formed over the fin layer, where the dummy gates are formed to taper from a smaller width at a top region of the dummy gates to a larger width at a bottom region of the dummy gates. Sidewall spacers are formed on sidewalls of the dummy gates. An interlayer dielectric is formed in regions between the dummy gates and contacts the sidewall spacers. The dummy gates are removed to form openings in the interlayer dielectric and to expose the sidewall spacers on sides of the openings in the interlayer dielectric. The sidewall spacers are etched at a greater rate at a top region of the sidewall spacers than at a bottom region of the sidewall spacers.

Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

Abstract: A method for adjusting the uniformity of a display is provided. The method includes the following steps. An angle sensor is disposed on a display. The display opposite to a measurement device is disposed on a rotation axis. The uniformity of a frame of the display at at least one use angle is measured by the measurement device, wherein the display is adjusted to a first use angle and is left still for a period of time, so that the uniformity of the display arranged at the first use angle has a first uniformity correction parameter; and a correspondence table relevant to the first use angle and the first uniformity correction parameter is stored to the display.

Abstract: A method of generating an integrated circuit includes providing a placing layout of the integrated circuit; generating a routed layout of the integrated circuit, the routed layout includes a layout region with a systematic design rule check (DRC) violation; generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in a plurality of placement recipes; extracting features of the placing layout to obtain an extracted data; extracting features of the layout region with the systematic DRC violation to obtain an extracted routing data; performing a training process upon the extracted data and the extracted routing data to generate a plurality of aggregated-cluster models; and selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models.

Abstract: A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.

Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.

Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.

Abstract: A semiconductor device may be formed by forming a first fin and a second fin in a first area and a second area of a substrate, respectively; which may be followed by forming of a first dummy gate structure and a second dummy gate structure straddling the first fin and second fin, respectively and forming a sacrificial layer extending along a bottom portion of the second dummy gate structure. The first dummy gate structure may be replaced with a first metal gate structure, while the second dummy gate structure and the sacrificial layer may be replaced with a second metal gate structure.

Abstract: A method for fabricating semiconductor devices includes forming a first semiconductor channel structure and a second semiconductor channel structure over a substrate; forming a metal gate structure, wherein the metal gate structure includes a first portion and a second portion straddling the first semiconductor channel structure and the second semiconductor channel structure, respectively; replacing a third portion of the metal gate structure between the first portion and the second portion with a first dielectric material to form a gate isolation structure, wherein a width of the gate isolation structure along the second direction decreases with an increasing depth of the gate isolation structure toward the substrate; and replacing a portion of the gate isolation structure, the second portion of the metal gate structure, and the second semiconductor channel structure with a second dielectric material to form an edge isolation structure.

Abstract: A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.

Abstract: A method and user device for determining a unified Parkinson's disease rating scale (UPDRS) value associated with a user of the user device include obtaining video data associated with a movement of a body part of the user. The UPDRS value is determined using a model and the video data associated with the movement of the body part of the user. The UPDRS value is provided to permit an evaluation of the user based on the UPDRS value.

Abstract: A method, computer program, and computer system are provided for image segmentation. Image data, such as biological image data, is received. One or more objects associated with the received image data is detected. One or more regions of interest are determined within the receive image data corresponding to one or more segments based on the detected objects.