Abstract: An electronic system test method, comprising: (a) inputting a victim test pattern to a victim signal path of a target electronic system and simultaneously inputting at least one aggressor test pattern to at least one aggressor signal path of the target electronic system, according to a major set of test patterns comprising a plurality of minor set of test patterns; (b) acquiring a output response corresponding to the step (a); and (c) after changing the victim test pattern or the aggressor test pattern, and after repeating the step (a) and the step (b) until all of the major test patterns set are used thereby acquiring a plurality of the output responses, determining a combination level according to the output responses. The victim test pattern is an X bit pattern and the aggressor test pattern is a Y bit pattern, X and Y are positive integers larger than or equal to 3.

Abstract: A method for providing an epitaxial layer of a first material over a substrate comprising a second material having a lattice constant different from that of the first material. In the method of the present invention, a first layer of the first material is grown on the substrate. A portion of the first layer is treated to render that portion amorphous. The amorphous portion is then annealed at a temperature above the recrystallization point of the amorphous portion, but below the melting point of the crystallized portion of the first layer thereby recrystallizing the amorphous portion of the first layer. The first layer may rendered amorphous by ion implantation. The method may be used to generate GaN layers on sapphire having fewer dislocations than GaN layers generated by conventional deposition techniques.