Abstract: A temperature sensor probe having a shaft is described. The shaft is made from a material that is corrosion resistant to plasma and remnants of a plasma process. The shaft extends over a portion of a metal layer, which forms a tip of the temperature sensor probe. The shaft further extends over a sleeve of the temperature sensor probe, a portion of a fiber optic medium of the temperature sensor probe and a portion of the fiber bundle housing of the temperature sensor probe. The material of the shaft increases a number of active processing hours for which the shaft is used within a plasma chamber during the plasma process.

Abstract: Systems, methods, and machine-readable and executable instructions are provided for preventing a memory attack to a wireless access point (AP). Preventing a memory attack to a wireless access point can include receiving, with a wireless AP, a generic advertisement service (GAS) initial request from a querying station and transmitting, with the wireless AP, a GAS initial response to the querying station without querying an advertisement server based on the GAS initial request.

Abstract: A system and method for a waferless cleaning method for a capacitive coupled plasma system. The method includes forming a protective layer on a top surface of an electrostatic chuck, volatilizing etch byproducts deposited on one or more inner surfaces of the plasma process chamber, removing volatilized etch byproducts from the plasma process chamber and removing the protective layer from the top surface of the electrostatic chuck. A capacitive coupled plasma system including a waferless cleaning recipe is also described.

Abstract: A system and method for a waferless cleaning method for a capacitive coupled plasma system. The method includes forming a protective layer on a top surface of an electrostatic chuck, volatilizing etch byproducts deposited on one or more inner surfaces of the plasma process chamber, removing volatilized etch byproducts from the plasma process chamber and removing the protective layer from the top surface of the electrostatic chuck. A capacitive coupled plasma system including a waferless cleaning recipe is also described.

Abstract: A system and method for a waferless cleaning method for a capacitive coupled plasma system. The method includes forming a protective layer on a top surface of an electrostatic chuck, volatilizing etch byproducts deposited on one or more inner surfaces of the plasma process chamber, removing volatilized etch byproducts from the plasma process chamber and removing the protective layer from the top surface of the electrostatic chuck. A capacitive coupled plasma system including a waferless cleaning recipe is also described.

Abstract: One or more aspects of this invention pertain to fabrication of electronic devices. One aspect of the present invention is a system for electroless deposition of metal on a substrate. According to one or more embodiments of the present invention, the system comprises a main subsystem in combination with one or more subsystems for electroless deposition on a substrate. Another aspect of the present invention is a method of making an electronic device. According to one or more embodiments of the present invention, the method comprises one or more processes. Descriptions according to one or more embodiments of the system and the processes are presented.

Abstract: One or more aspects of this invention pertain to fabrication of electronic devices. One aspect of the present invention is a system for electroless deposition of metal on a substrate. According to one or more embodiments of the present invention, the system comprises a main subsystem in combination with one or more subsystems for electroless deposition on a substrate. Another aspect of the present invention is a method of making an electronic device. According to one or more embodiments of the present invention, the method comprises one or more processes. Descriptions according to one or more embodiments of the system and the processes are presented.

Abstract: A first request is sent from a station to an access point. The station receives a first response from the access point that includes a first sequence number, and stores the first sequence number. The station sends a second request to the access point and sets a waiting period for receiving a response from the access point. The station receives a second response from the access point and a third response from a second access point during the waiting period. The second response includes a second sequence number and the third response includes a third sequence number. The station determines that the second response is a legitimate response by comparing the second and third sequence numbers to the first sequence number.

Abstract: A first request is sent from a station to an access point. The station receives a first response from the access point that includes a first sequence number, and stores the first sequence number. The station sends a second request to the access point and sets a waiting period for receiving a response from the access point. The station receives a second response from the access point and a third response from a second access point during the waiting period. The second response includes a second sequence number and the third response includes a third sequence number. The station determines that the second response is a legitimate response by comparing the second and third sequence numbers to the first sequence number.

Abstract: Systems, methods, and machine-readable and executable instructions are provided for preventing an input/output blocking attack to a wireless access point. Prevention can include instructions to receive a first comeback request from a querying station and to transmit a first portion of a response in a first comeback response frame including an indication of a comeback delay. Prevention can include instructions to receive a second comeback request from the querying station and transmit a second portion of the response in a second comeback response frame in response to the second comeback request complying with the comeback delay. Prevention can include instructions to drop the second comeback request from the querying station in response to the second comeback request not complying with the comeback delay.

Abstract: Systems, methods, and machine-readable and executable instructions are provided for preventing a memory attack to a wireless access point (AP). Preventing a memory attack to a wireless access point can include receiving, with a wireless AP, a generic advertisement service (GAS) initial request from a querying station and transmitting, with the wireless AP, a GAS initial response to the querying station without querying an advertisement server based on the GAS initial request.

Abstract: A system and method for a waferless cleaning method for a capacitive coupled plasma system. The method includes forming a protective layer on a top surface of an electrostatic chuck, volatilizing etch byproducts deposited on one or more inner surfaces of the plasma process chamber, removing volatilized etch byproducts from the plasma process chamber and removing the protective layer from the top surface of the electrostatic chuck. A capacitive coupled plasma system including a waferless cleaning recipe is also described.

Abstract: One embodiment of the present invention is a method of fabricating an integrated circuit. The method includes providing a substrate having a metal and dielectric damascene metallization layer and depositing substantially on the metal a cap. After deposition of the cap, the substrate is cleaned with a solution comprising an amine to provide a pH for the cleaning solution of 7 to about 13. Another embodiment of the presented invention is a method of cleaning substrates. Still another embodiment of the present invention is a formulation for a cleaning solution.

Abstract: Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.

Abstract: Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.

Abstract: Methods and solutions for preventing the formation of metal particulate defect matter upon a substrate after plating processes are provided. In particular, solutions are provided which are free of oxidizing agents and include a non-metal pH adjusting agent in sufficient concentration such that the solution has a pH between approximately 7.5 and approximately 12.0. In some cases, a solution may include a chelating agent. In addition or alternatively, a solution may include at least two different types of complexing agents each offering a single point of attachment for binding metal ions via respectively different functional groups. In any case, at least one of the complexing agents or the chelating agent includes a non-amine or non-imine functional group. An embodiment of a method for processing a substrate includes plating a metal layer upon the substrate and subsequently exposing the substrate to a solution comprising the aforementioned make-up.

Abstract: Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: One embodiment of the present invention is a method of fabricating an integrated circuit. The method includes providing a substrate having a metal and dielectric damascene metallization layer and depositing substantially on the metal a cap. After deposition of the cap, the substrate is cleaned with a solution comprising an amine to provide a pH for the cleaning solution of 7 to about 13. Another embodiment of the presented invention is a method of cleaning substrates. Still another embodiment of the present invention is a formulation for a cleaning solution.

Abstract: Presented are methods and systems for fabricating three-dimensional integrated circuits having large diameter through-hole vias. One embodiment of the present invention provides a method of processing a wafer having holes for through-hole vias. The method comprises plating a gapfill metal on the wafer. The method also comprises chemically or electrochemically deplating a portion of the overburden metal. The method further comprises using chemical mechanical planarization to planarize the gapfill metal and to remove the remaining overburden metal. Another embodiment of the present invention is an integrated system comprising a process chamber for containing the wafer, a plating component integrated with the process chamber, and a deplating component integrated with the process chamber. The plating component is configured to electrochemically plate a gapfill metal onto the wafer to a least partially fill the holes.

Abstract: Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.