Abstract: A circuit layout structure includes a metal interlayer dielectric layer surrounding a metal interconnect and a metal pattern within a scrub line. The scrub line is in the vicinity of the metal interlayer dielectric layer and the metal interconnect. The metal pattern or the metal interconnect are suitably segregated to reduce a capacitance charging effect.

Abstract: A method for forming an opening is disclosed. First, a semiconductor substrate is provided, in which the semiconductor substrate includes at least one metal interconnects therein. A stacked film is formed on the semiconductor substrate, in which the stacked film includes at least one dielectric layer and one hard mask. The hard mask is used to form an opening in the stacked film without exposing the metal interconnects, and the hard mask is removed thereafter. A barrier layer is later deposited on the semiconductor substrate to cover a portion of the dielectric layer and the surface of the metal interconnects.

Abstract: A circuit layout structure includes a metal interlayer dielectric layer surrounding a metal interconnect and a metal pattern within a scrub line. The scrub line is in the vicinity of the metal interlayer dielectric layer and the metal interconnect. The metal pattern or the metal interconnect are suitably segregated to reduce a capacitance charging effect.

Abstract: A method of etching a multi-layer is provided. The multi-layer includes an aluminum layer disposed on a semiconductor substrate and an anti-reflection coating layer disposed on the aluminum layer. The method includes: performing a first etching process to etch the anti-reflection coating layer by providing a first etching gas, wherein the first etching gas includes a chlorine-containing substance; then performing a second etching process to etch the aluminum layer by providing a second etching gas, wherein the second etching gas does not include a chlorine-containing compound.

Abstract: A rework method of a metal hard mask layer is provided. First, a material layer is provided. A dielectric layer, a first metal hard mask layer, and a patterned first dielectric hard mask layer have been sequentially formed on the material layer. There is a defect on a region of the first metal hard mask layer, and therefore the region of the first metal hard mask layer is not able to be patterned. After that, the patterned first dielectric hard mask layer and the first metal hard mask layer are removed. A planarization process is then performed on the dielectric layer. Next, a second metal hard mask layer and a second dielectric hard mask layer are sequentially formed on the dielectric layer.

Abstract: An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening.

Abstract: A method for forming an opening is disclosed. First, a semiconductor substrate is provided, in which the semiconductor substrate includes at least one metal interconnects therein. A stacked film is formed on the semiconductor substrate, in which the stacked film includes at least one dielectric layer and one hard mask. The hard mask is used to form an opening in the stacked film without exposing the metal interconnects, and the hard mask is removed thereafter. A barrier layer is later deposited on the semiconductor substrate to cover a portion of the dielectric layer and the surface of the metal interconnects.

Abstract: A two-step method for etching a fuse window on a semiconductor substrate is provided. A semiconductor substrate having thereon a fuse interconnect-wire is formed in a dielectric film stack. The dielectric film stack includes a target dielectric layer overlying said fuse interconnect-wire, an intermediate dielectric layer and a passivation layer. A photoresist layer is formed on the passivation layer with an opening that defines said fuse window. A first dry etching process is performed to non-selectively etch the passivation layer and the intermediate dielectric layer through the opening thereby exposing the target dielectric layer. The thickness of the target dielectric layer after the first dry etching process is then measured. An APC-controlled second dry etching process is performed to etch a portion of the exposed target dielectric layer, thereby reliably forming the fuse window.

Abstract: An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening.

Abstract: An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening.

Abstract: A two-step method for etching a fuse window on a semiconductor substrate is provided. A semiconductor substrate having thereon a fuse interconnect-wire is formed in a dielectric film stack. The dielectric film stack includes a target dielectric layer overlying said fuse interconnect-wire, an intermediate dielectric layer and a passivation layer. A photoresist layer is formed on the passivation layer with an opening that defines said fuse window. A first dry etching process is performed to non-selectively etch the passivation layer and the intermediate dielectric layer through the opening thereby exposing the target dielectric layer. The thickness of the target dielectric layer after the first dry etching process is then measured. An APC-controlled second dry etching process is performed to etch a portion of the exposed target dielectric layer, thereby reliably forming the fuse window.