Patents by Inventor Shin-Ae Lee
Shin-Ae Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10696296Abstract: Disclosed herein are a vehicle control apparatus and a method for controlling a vehicle using the same. The vehicle control apparatus according to an embodiment of the present invention includes an input unit that receives handle operation information detected by a sensing device, receives avoidance steering information of a driver, and receives behavior information of a vehicle, a determination unit that determines whether the vehicle is in an emergency steering avoidance state based on the received handle operation information, the received avoidance steering information of the driver, and the received behavior information of the vehicle, and a control unit that controls an evasive handling control (EHC) system and an electronic stability control (ESC) system such that the EHC system presses wheels in advance ahead of the ESC system to perform a braking operation according to a target wheel pressure value, when the vehicle is in the emergency steering avoidance state.Type: GrantFiled: October 11, 2017Date of Patent: June 30, 2020Assignee: MANDO CORPORATIONInventor: Shin-Ae Lee
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Publication number: 20180099664Abstract: Disclosed herein are a vehicle control apparatus and a method for controlling a vehicle using the same. The vehicle control apparatus according to an embodiment of the present invention includes an input unit that receives handle operation information detected by a sensing device, receives avoidance steering information of a driver, and receives behavior information of a vehicle, a determination unit that determines whether the vehicle is in an emergency steering avoidance state based on the received handle operation information, the received avoidance steering information of the driver, and the received behavior information of the vehicle, and a control unit that controls an evasive handling control (EHC) system and an electronic stability control (ESC) system such that the EHC system presses wheels in advance ahead of the ESC system to perform a braking operation according to a target wheel pressure value, when the vehicle is in the emergency steering avoidance state.Type: ApplicationFiled: October 11, 2017Publication date: April 12, 2018Inventor: Shin-Ae LEE
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Patent number: 7871914Abstract: A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.Type: GrantFiled: April 28, 2009Date of Patent: January 18, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Ho Kim, Chang-Sub Lee, Jeong-Dong Choe, Sung-Min Kim, Shin-Ae Lee, Dong-Gun Park
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Patent number: 7615429Abstract: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.Type: GrantFiled: November 30, 2007Date of Patent: November 10, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Kim, Dong-Gun Park, Chang-Sub Lee, Jeong-Dong Choe, Shin-Ae Lee, Seong-Ho Kim
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Publication number: 20090215238Abstract: A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.Type: ApplicationFiled: April 28, 2009Publication date: August 27, 2009Inventors: Seong-Ho Kim, Chang-Sub Lee, Jeong-Dong Choe, Sung-Min Kim, Shin-Ae Lee, Dong-Gun Park
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Patent number: 7541645Abstract: A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.Type: GrantFiled: August 31, 2006Date of Patent: June 2, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Kim, Dong-Gun Park, Sung-Young Lee, Hye-Jin Cho, Eun-Jung Yun, Shin-Ae Lee, Chang-Woo Oh, Jeong-Dong Choe
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Patent number: 7541656Abstract: A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.Type: GrantFiled: November 3, 2006Date of Patent: June 2, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Ho Kim, Chang-Sub Lee, Jeong-Dong Choe, Sung-Min Kim, Shin-Ae Lee, Dong-Gun Park
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Patent number: 7534707Abstract: MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in the substrate. First and second lateral protrusions extend from the lower portions of respective sidewalls of the gate electrode. The drain region has a first lightly-doped drain region under the first lateral protrusion, a second lightly-doped drain region adjacent the first lightly-doped drain region, and a heavily-doped drain region adjacent to the second lightly-doped drain region. The source region similarly has a first lightly-doped source region under the second lateral protrusion, a second lightly-doped source region adjacent the first lightly-doped source region, and a heavily-doped source region adjacent to the second lightly-doped source region. The second lightly-doped regions are deeper than the first lightly-doped regions, and the gate electrode may have an inverted T-shape.Type: GrantFiled: November 16, 2006Date of Patent: May 19, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Shin-Ae Lee, Dong-gun Park, Chang-sub Lee, Jeong-dong Choe, Sung-min Kim, Seong-ho Kim
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Patent number: 7473963Abstract: Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.Type: GrantFiled: September 13, 2007Date of Patent: January 6, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Kim, Dong-Won Kim, Eun-Jung Yun, Dong-Gun Park, Sung-Young Lee, Jeong-Dong Choe, Shin-Ae Lee, Hye-Jin Cho
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Patent number: 7397131Abstract: A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.Type: GrantFiled: April 3, 2006Date of Patent: July 8, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Ho Kim, Dong-Gun Park, Chang-Sub Lee, Jeong-Dong Choe, Sung-Min Kim, Shin-Ae Lee
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Patent number: 7381601Abstract: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.Type: GrantFiled: May 7, 2004Date of Patent: June 3, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Kim, Dong-Gun Park, Chang-Sub Lee, Jeong-Dong Choe, Shin-Ae Lee, Seong-Ho Kim
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Publication number: 20080090362Abstract: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.Type: ApplicationFiled: November 30, 2007Publication date: April 17, 2008Inventors: Sung-Min Kim, Dong-Gun Park, Chang-Sub Lee, Jeong-Dong Choe, Shin-Ae Lee, Seong-Ho Kim
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Publication number: 20080001218Abstract: Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.Type: ApplicationFiled: September 13, 2007Publication date: January 3, 2008Inventors: Sung-Min Kim, Dong-Won Kim, Eun-Jung Yun, Dong-Gun Park, Sung-Young Lee, Jeong-Dong Choe, Shin-Ae Lee, Hye-Jin Cho
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Patent number: 7285466Abstract: Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.Type: GrantFiled: August 2, 2004Date of Patent: October 23, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Kim, Dong-Won Kim, Eun-Jung Yun, Dong-Gun Park, Sung-Young Lee, Jeong-Dong Choe, Shin-Ae Lee, Hye-Jin Cho
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Publication number: 20070096217Abstract: MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in the substrate. First and second lateral protrusions extend from the lower portions of respective sidewalls of the gate electrode. The drain region has a first lightly-doped drain region under the first lateral protrusion, a second lightly-doped drain region adjacent the first lightly-doped drain region, and a heavily-doped drain region adjacent to the second lightly-doped drain region. The source region similarly has a first lightly-doped source region under the second lateral protrusion, a second lightly-doped source region adjacent the first lightly-doped source region, and a heavily-doped source region adjacent to the second lightly-doped source region. The second lightly-doped regions are deeper than the first lightly-doped regions, and the gate electrode may have an inverted T-shape.Type: ApplicationFiled: November 16, 2006Publication date: May 3, 2007Inventors: Shin-Ae Lee, Dong-gun Park, Chang-sub Lee, Jeong-dong Choe, Sung-min Kim, Seong-ho Kim
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Publication number: 20070057288Abstract: A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.Type: ApplicationFiled: November 3, 2006Publication date: March 15, 2007Inventors: Seong-Ho Kim, Chang-Sub Lee, Jeong-Dong Choe, Sung-Min Kim, Shin-Ae Lee, Dong-Gun Park
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Publication number: 20060289907Abstract: A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.Type: ApplicationFiled: August 31, 2006Publication date: December 28, 2006Inventors: Sung-Min Kim, Dong-Gun Park, Sung-Young Lee, Hye-Jin Cho, Eun-Jung Yun, Shin-Ae Lee, Chang-Woo Oh, Jeong-Dong Choe
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Patent number: 7154154Abstract: MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in the substrate. First and second lateral protrusions extend from the lower portions of respective sidewalls of the gate electrode. The drain region has a first lightly-doped drain region under the first lateral protrusion, a second lightly-doped drain region adjacent the first lightly-doped drain region, and a heavily-doped drain region adjacent to the second lightly-doped drain region. The source region similarly has a first lightly-doped source region under the second lateral protrusion, a second lightly-doped source region adjacent the first lightly-doped source region, and a heavily-doped source region adjacent to the second lightly-doped source region. The second lightly-doped regions are deeper than the first lightly-doped regions, and the gate electrode may have an inverted T-shape.Type: GrantFiled: October 10, 2003Date of Patent: December 26, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Shin-Ae Lee, Dong-gun Park, Chang-sub Lee, Jeong-dong Choe, Sung-min Kim, Seong-ho Kim
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Patent number: 7148527Abstract: A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.Type: GrantFiled: December 17, 2003Date of Patent: December 12, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Ho Kim, Chang-Sub Lee, Jeong-Dong Choe, Sung-Min Kim, Shin-Ae Lee, Dong-Gun Park
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Patent number: 7132349Abstract: An integrated circuit structure can include an isolation structure that electrically isolates an active region of an integrated circuit substrate from adjacent active regions and an insulation layer that extends from the isolation structure to beneath the active region. An epitaxial silicon layer extends from the active region through the insulation layer to a substrate beneath the insulation layer.Type: GrantFiled: January 19, 2006Date of Patent: November 7, 2006Assignee: Samsung Electronics Co. Ltd.Inventors: Sung-min Kim, Dong-gun Park, Chang-sub Lee, Jeong-dong Choe, Shin-ae Lee, Seong-ho Kim