Patents by Inventor Shin Chen Lin
Shin Chen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990418Abstract: A method for forming a chip package structure is provided. The method includes removing a first portion of a substrate to form a first recess in the substrate. The method includes forming a buffer structure in the first recess. A first Young's modulus of the buffer structure is less than a second Young's modulus of the substrate. The method includes forming a first wiring structure over the buffer structure and the substrate. The method includes bonding a chip package to the first wiring structure. The chip package has an interposer substrate and a chip structure over the interposer substrate, and a first corner of the interposer substrate and a second corner of the chip structure overlap the buffer structure in a top view of the chip package and the buffer structure.Type: GrantFiled: August 27, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Hua Wang, Po-Chen Lai, Ping-Tai Chen, Che-Chia Yang, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11984381Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier substrate, an interposer substrate, a semiconductor device, a lid, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate. The lid is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the lid and the semiconductor device. A first recess is formed on a lower surface of the lid facing the semiconductor device, and the first recess overlaps the semiconductor device in a top view.Type: GrantFiled: November 16, 2021Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chen Lai, Ming-Chih Yew, Po-Yao Lin, Chin-Hua Wang, Shin-Puu Jeng
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Patent number: 11978722Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate. The chip structure has an inclined sidewall, the inclined sidewall is at an acute angle to a vertical, the vertical is a direction perpendicular to a main surface of the chip structure, and the acute angle is in a range from about 12 degrees to about 45 degrees. The method also includes forming a protective layer to surround the chip structure.Type: GrantFiled: August 27, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Shen Yeh, Po-Chen Lai, Che-Chia Yang, Li-Ling Liao, Po-Yao Lin, Shin-Puu Jeng
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Publication number: 20240136246Abstract: A semiconductor device includes a package structure, a first heat spreader, and a second heat spreader. The first heat spreader is aside the package structure. The second heat spreader is in physical contact with the first heat spreader. The second heat spreader covers a top surface and sidewalls of the package structure. A material of the first heat spreader is different from a material of the second heat spreader.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
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Patent number: 11967547Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.Type: GrantFiled: August 26, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Hua Wang, Shu-Shen Yeh, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11967582Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.Type: GrantFiled: April 24, 2023Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chin-Hua Wang, Po-Chen Lai, Shu-Shen Yeh, Tsung-Yen Lee, Po-Yao Lin, Shin-Puu Jeng
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Publication number: 20240088095Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: Chin-Hua WANG, Shin-Puu JENG, Po-Yao LIN, Po-Chen LAI, Shu-Shen YEH, Ming-Chih YEW, Yu-Sheng LIN
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Patent number: 11915991Abstract: A semiconductor device includes a substrate, a package structure, a first heat spreader, and a second heat spreader. The package structure is disposed on the substrate. The first heat spreader is disposed on the substrate. The first heat spreader surrounds the package structure. The second heat spreader is disposed on the package structure. The second heat spreader is connected to the first heat spreader. A material of the first heat spreader is different from a material of the second heat spreader.Type: GrantFiled: June 29, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
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Publication number: 20220320289Abstract: High-voltage semiconductor device and method of forming the same, the high-voltage semiconductor device includes a substrate, a gate structure, a drain, a first insulating structure and a drain doped region. The gate structure is disposed on the substrate. The drain is disposed in the substrate, at one side of the gate structure. The first insulating structure is disposed on the substrate, under the gate structure to partially overlap with the gate structure. The drain doped region is disposed in the substrate, under the drain and the first insulating structure, and the drain doped region includes a discontinuous bottom surface.Type: ApplicationFiled: June 22, 2022Publication date: October 6, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Wen-Hsin Lin, Shin-Chen Lin, Yu-Hao Ho, Cheng-Tsung Wu, Chiu-Hao Chen
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Publication number: 20220293779Abstract: A high electron mobility transistor includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate field plate, a source electrode, at least one first field plate, and a second field plate. The gate field plate is disposed on the semiconductor barrier layer. The source electrode is disposed on one side of the gate field plate, and the first field plate is disposed on the other side of the gate field plate and laterally spaced apart from the gate field plate. The second field plate covers the gate field plate and the first field plate and is electrically connected to the source electrode, where the area of the second field plate is larger than the sum of the area of the gate field plate and the area of the first field plate when perceived from a top-down perspective.Type: ApplicationFiled: March 15, 2021Publication date: September 15, 2022Inventors: Yang Du, Shin-Chen Lin, Chia-Ching Huang
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Patent number: 11398552Abstract: High-voltage semiconductor device and method of forming the same, the high-voltage semiconductor device includes a substrate, a gate structure, a drain, a first insulating structure and a drain doped region. The gate structure is disposed on the substrate. The drain is disposed in the substrate, at one side of the gate structure. The first insulating structure is disposed on the substrate, under the gate structure to partially overlap with the gate structure. The drain doped region is disposed in the substrate, under the drain and the first insulating structure, and the drain doped region includes a discontinuous bottom surface.Type: GrantFiled: August 26, 2020Date of Patent: July 26, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Wen-Hsin Lin, Shin-Chen Lin, Yu-Hao Ho, Cheng-Tsung Wu, Chiu-Hao Chen
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Publication number: 20220069081Abstract: High-voltage semiconductor device and method of forming the same, the high-voltage semiconductor device includes a substrate, a gate structure, a drain, a first insulating structure and a drain doped region. The gate structure is disposed on the substrate. The drain is disposed in the substrate, at one side of the gate structure. The first insulating structure is disposed on the substrate, under the gate structure to partially overlap with the gate structure. The drain doped region is disposed in the substrate, under the drain and the first insulating structure, and the drain doped region includes a discontinuous bottom surface.Type: ApplicationFiled: August 26, 2020Publication date: March 3, 2022Inventors: Wen-Hsin Lin, Shin-Chen Lin, Yu-Hao Ho, Cheng-Tsung Wu, Chiu-Hao Chen
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Publication number: 20020068425Abstract: A method for bumping and backlapping a semiconductor wafer that has a multiplicity of solder bumps formed on an active surface of the wafer is disclosed. In the method, a preprocessed wafer that has a multiplicity of bond pads formed on a top surface is first provided, a under-bump-metallurgy (UBM) layer is then sputter deposited on top of the wafer surface, followed by the lamination of a dry film resist layer on top of the UBM layer. The dry film resist layer is then patterned with a multiplicity of openings exposing the multiplicity of bond pads, followed by the deposition of a solder material into the multiplicity of openings to form the solder bumps. A protective tape is then adhesively bonded to the top of the dry film resist layer before the wafer is positioned into a backlapping apparatus for removing of a preselected thickness from the backside of the wafer.Type: ApplicationFiled: December 1, 2000Publication date: June 6, 2002Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Yen-Ming Chen, Kuo-Wei Lin, Cheng-Yu Chu, Fu-Jier Fan, Yang-Tung Fan, Chiou-Shian Peng, Shin Chen Lin