Patents by Inventor Shin-Chi Chen
Shin-Chi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240142301Abstract: The present disclosure provides a sensing circuit, including a photo-sensing component, a first transistor, and a temperature-sensing component. The photo-sensing component is configured to receive a light and transmit a first current according to an intensity of the light. A gate terminal of the first transistor is configured to receive a first control circuit. The photo-sensing component and the first transistor are coupled in series between first and second nodes. The temperature-sensing component is coupled between the first and second nodes and is configured to generate a second current according to a temperature. The temperature-sensing component includes a channel structure, a first gate, a second gate, and a light-shielding structure. The channel structure is configured to transmit the second current.Type: ApplicationFiled: December 14, 2022Publication date: May 2, 2024Inventors: Ming-Yao CHEN, Chang-Hung LI, Shin-Shueh CHEN, Jui-Chi LO
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Publication number: 20240146205Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.Type: ApplicationFiled: September 23, 2023Publication date: May 2, 2024Inventors: Shin-Li Lin, He-Yi Shu, Shih-Jen Yang, Ta-Yung Yang, Yi-Min Shiu, Chih-Ching Lee, Yu-Chieh Hsieh, Chao-Chi Chen
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Patent number: 11971298Abstract: The present disclosure provides a sensing circuit, including a photo-sensing component, a first transistor, and a temperature-sensing component. The photo-sensing component is configured to receive a light and transmit a first current according to an intensity of the light. A gate terminal of the first transistor is configured to receive a first control circuit. The photo-sensing component and the first transistor are coupled in series between first and second nodes. The temperature-sensing component is coupled between the first and second nodes and is configured to generate a second current according to a temperature. The temperature-sensing component includes a channel structure, a first gate, a second gate, and a light-shielding structure. The channel structure is configured to transmit the second current.Type: GrantFiled: December 14, 2022Date of Patent: April 30, 2024Assignee: AUO CORPORATIONInventors: Ming-Yao Chen, Chang-Hung Li, Shin-Shueh Chen, Jui-Chi Lo
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Patent number: 11764174Abstract: A semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer is provided. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer.Type: GrantFiled: November 23, 2021Date of Patent: September 19, 2023Assignee: United Microelectronics Corp.Inventors: Chun-Chi Huang, Hui-Lung Chou, Chuang-Han Hsieh, Yung-Feng Lin, Shin-Chi Chen
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Publication number: 20230237238Abstract: A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.Type: ApplicationFiled: April 3, 2023Publication date: July 27, 2023Inventors: Shin-Chi Chen, King-Ho Tam, Yu-Ze Lin, Huang-Yu Chen
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Publication number: 20230136978Abstract: A semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer is provided. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer.Type: ApplicationFiled: November 23, 2021Publication date: May 4, 2023Applicant: United Microelectronics Corp.Inventors: Chun-Chi Huang, Hui-Lung Chou, Chuang-Han Hsieh, Yung-Feng Lin, Shin-Chi Chen
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Patent number: 11620426Abstract: A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device. A computer system including one or more EDAs configured to perform the method is also disclosed.Type: GrantFiled: May 27, 2021Date of Patent: April 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shin-Chi Chen, King-Ho Tam, Yu-Ze Lin, Huang-Yu Chen
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Publication number: 20220382946Abstract: A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device. A computer system including one or more EDAs configured to perform the method is also disclosed.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Inventors: Shin-Chi Chen, King-Ho Tam, Yu-Ze Lin, Huang-Yu Chen
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Patent number: 10699913Abstract: Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.Type: GrantFiled: December 13, 2018Date of Patent: June 30, 2020Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Shin-Chi Chen, Jiunn-Hsiung Liao, Yu-Tsung Lai
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Publication number: 20190131142Abstract: Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.Type: ApplicationFiled: December 13, 2018Publication date: May 2, 2019Inventors: Shin-Chi CHEN, Jiunn-Hsiung LIAO, Yu-Tsung LAI
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Patent number: 10276443Abstract: A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.Type: GrantFiled: February 28, 2017Date of Patent: April 30, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shin-Chi Chen, Chih-Chung Chen, An-Chi Liu, Chih-Yueh Li, Pei-Ching Yeh, Tsung-Chieh Yang
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Patent number: 10199232Abstract: Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.Type: GrantFiled: February 24, 2011Date of Patent: February 5, 2019Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Shin-Chi Chen, Jiunn-Hsiung Liao, Yu-Tsung Lai
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Publication number: 20180226403Abstract: A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.Type: ApplicationFiled: February 28, 2017Publication date: August 9, 2018Inventors: Shin-Chi Chen, Chih-Chung Chen, An-Chi Liu, Chih-Yueh Li, Pei-Ching Yeh, Tsung-Chieh Yang
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Patent number: 9748333Abstract: A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy region defined on the substrate, and a gate electrode formed on the substrate. The dummy region is formed between the I/O region and the core region. The gate electrode crosses the I/O region and covers a portion of the dummy region.Type: GrantFiled: December 26, 2014Date of Patent: August 29, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shin-Chi Chen, Chih-Yueh Li, Pei-Ching Yeh, Chih-Jen Lin
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Publication number: 20160148878Abstract: A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy region defined on the substrate, and a gate electrode formed on the substrate. The dummy region is formed between the I/O region and the core region. The gate electrode crosses the I/O region and covers a portion of the dummy region.Type: ApplicationFiled: December 26, 2014Publication date: May 26, 2016Inventors: Shin-Chi Chen, Chih-Yueh Li, Pei-Ching Yeh, Chih-Jen Lin
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Patent number: 9318571Abstract: A gate structure includes a gate disposed on a substrate, a first spacer disposed on the substrate and surrounding the gate and a second spacer disposed on the first spacer and surrounding the gate, the second spacer is lower than the first spacer.Type: GrantFiled: February 23, 2009Date of Patent: April 19, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: I-Chang Wang, Ming-Tsung Chen, Ling-Chun Chou, Po-Chao Tsao, Tsung-Hung Chang, Hui-Ling Chen, Cheng-Yen Wu, Chieh-Te Chen, Shin-Chi Chen
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Patent number: 9312258Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.Type: GrantFiled: July 8, 2013Date of Patent: April 12, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Guang-Yaw Hwang, Ling-Chun Chou, I-Chang Wang, Shin-Chuan Huang, Jiunn-Hsiung Liao, Shin-Chi Chen, Pau-Chung Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chieh-Te Chen
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Patent number: 9305847Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.Type: GrantFiled: June 25, 2014Date of Patent: April 5, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shin-Chi Chen, Chih-Yueh Li, Shui-Yen Lu, Chi-Mao Hsu, Yuan-Chi Pai, Yu-Hong Kuo, Nien-Ting Ho
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Patent number: 9245972Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate.Type: GrantFiled: September 3, 2013Date of Patent: January 26, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shin-Chi Chen, Chih-Yueh Li, Shui-Yen Lu, Yuan-Chi Pai, Fong-Lung Chuang
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Publication number: 20150380312Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.Type: ApplicationFiled: June 25, 2014Publication date: December 31, 2015Inventors: Shin-Chi Chen, Chih-Yueh Li, Shui-Yen Lu, Chi-Mao Hsu, Yuan-Chi Pai, Yu-Hong Kuo, Nien-Ting Ho