Patents by Inventor Shin Egami

Shin Egami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11468084
    Abstract: An information processing device for processing target data according to one or more embodiments may include a preprocessor and a preprocess ID assigner. The preprocessor may be configured to generate preprocessed data by performing at least one preprocess on the target data. The preprocess ID assigner may be configured to assign, to the preprocessed data, a preprocess ID corresponding to the at least one preprocess.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: October 11, 2022
    Assignee: OMRON Corporation
    Inventors: Shin Egami, Kazuki Kasai, Tomohiro Taguchi
  • Publication number: 20210248156
    Abstract: An information processing device for processing target data according to one or more embodiments may include a preprocessor and a preprocess ID assigner. The preprocessor may be configured to generate preprocessed data by performing at least one preprocess on the target data. The preprocess ID assigner may be configured to assign, to the preprocessed data, a preprocess ID corresponding to the at least one preprocess.
    Type: Application
    Filed: March 11, 2019
    Publication date: August 12, 2021
    Applicant: OMRON Corporation
    Inventors: Shin EGAMI, Kazuki KASAI, Tomohiro TAGUCHI
  • Publication number: 20190181025
    Abstract: A monitoring system according to an aspect may construct a predictive model that predicts a value of a removal amount depending on values of an accumulated operating time and an accumulated number of processed wafers, based on learning data; acquires actual values of the accumulated operating time, the accumulated number of processed wafers, and the removal amount with respect to a wet etching apparatus when it is in operation; calculates a predicted value of the removal amount by inputting the acquired actual values of the accumulated operating time and the accumulated number of processed wafers to the predictive model; calculates the difference between the predicted value and the actual value of the removal amount, as an indicator value serving as a measure of how necessary it is to replace a chemical solution; and outputs information regarding replacement of the chemical solution based on the calculated indicator value.
    Type: Application
    Filed: September 17, 2018
    Publication date: June 13, 2019
    Applicant: OMRON Corporation
    Inventors: Yuya OTA, Toru FUJII, Shin EGAMI, Kosuke TSURUTA, Hiroki KOYAMA
  • Patent number: 8035131
    Abstract: A method for forming a nitride semiconductor laminated structure includes forming a first layer that is an n-type or i-type first layer composed of a group III nitride semiconductor using an H2 carrier gas; forming a second layer by laminating a p-type second layer composed of a group III nitride semiconductor and containing Mg on the first layer using an H2 carrier gas; and forming a third layer that is an n-type or i-type third layer composed of a group III nitride semiconductor on the second layer using an H2 carrier gas after forming the second layer. A method for manufacturing a nitride semiconductor device includes the method steps for forming the nitride semiconductor laminated structure.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: October 11, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Hirotaka Otake, Hiroaki Ohta, Shin Egami
  • Publication number: 20100078688
    Abstract: A nitride semiconductor device of the present invention includes: a nitride semiconductor laminated structure including an n-type first layer, a second layer that is laminated on the first layer and contains a p-type impurity, and an n-type third layer laminated on the second layer, each layer of the nitride semiconductor laminated structure being made of a Group III nitride semiconductor, and having a wall surface extending from the first, second, to third layers; a fourth layer that is formed on the wall surface in the second layer and that has a different conductive characteristic from that of the second layer; a gate insulating film formed to contact the fourth layer; and a gate electrode formed as facing the fourth layer with the gate insulating film being sandwiched between the gate electrode and the fourth layer.
    Type: Application
    Filed: January 16, 2008
    Publication date: April 1, 2010
    Applicant: ROHM CO., LTD
    Inventors: Hirotaka Otake, Shin Egami, Hiroaki Ohta
  • Publication number: 20100047976
    Abstract: The method for forming a nitride semiconductor laminated structure according to the present invention includes: a first layer forming step of forming an n-type or i-type first layer composed of a group III nitride semiconductor; a second layer forming step of laminating a p-type second layer composed of a group III nitride semiconductor and containing Mg on the first layer; and a third layer forming step of forming an n-type or i-type third layer composed of a group III nitride semiconductor on the second layer after the second layer forming step.
    Type: Application
    Filed: March 7, 2008
    Publication date: February 25, 2010
    Applicant: ROHM CO., LTD
    Inventors: Hirotaka Otake, Hiroaki Ohta, Shin Egami
  • Publication number: 20080203471
    Abstract: The nitride semiconductor device includes: a nitride semiconductor structure comprising an n-type first layer, a p-type second layer, and an n-type third layer, the nitride semiconductor structure comprising a mesa structure having a lateral surface which forms a wall surface extending from the first, second, to third layers; a gate insulating film formed on the wall surface of the mesa structure; a gate electrode formed as facing the wall surface in the second layer; a drain electrode electrically connected to the first layer; and a source electrode electrically connected to the third layer, the nitride semiconductor structure having a high dislocation region and a low dislocation region arranged along a direction parallel to a principal surface of lamination of the nitride semiconductor structure, a dislocation density of the low dislocation region being lower than that of the high dislocation region, the mesa structure being formed in the low dislocation region.
    Type: Application
    Filed: February 25, 2008
    Publication date: August 28, 2008
    Applicant: ROHM CO., LTD.
    Inventors: Hirotaka Otake, Shin Egami, Hiroaki Ohta