Abstract: According to embodiments, an image drawing apparatus includes: an SRAM; and a transaction conversion unit configured to convert a transaction based on a virtual address indicating a pixel position in a storage area of the SRAM into a transaction based on a physical address in the SRAM. When the storage area is divided into a plurality of windows in a row direction and a column direction so that each window includes one or more lines, and an assigned area which is assigned the physical address in the SRAM is set in each of the windows, the transaction conversion unit converts the transaction based on the virtual address into the transaction based on the physical address based on whether the pixel position indicated by the virtual address is in the assigned area.

Abstract: According to embodiments, an image drawing apparatus includes: an SRAM; and a transaction conversion unit configured to convert a transaction based on a virtual address indicating a pixel position in a storage area of the SRAM into a transaction based on a physical address in the SRAM. When the storage area is divided into a plurality of windows in a row direction and a column direction so that each window includes one or more lines, and an assigned area which is assigned the physical address in the SRAM is set in each of the windows, the transaction conversion unit converts the transaction based on the virtual address into the transaction based on the physical address based on whether the pixel position indicated by the virtual address is in the assigned area.

Abstract: A clock distribution circuit for distributing an input clock according to an embodiment of the present invention includes: a first clock buffer receiving the clock; a first clock mask series-connected to the first clock buffer and controlling clock input to the first clock buffer; a second clock buffer series-connected to the first clock buffer and receiving a clock output from the first clock mask; and a second clock mask series-connected to the first clock buffer and the second clock buffer to control clock input to the second clock buffer.

Abstract: A clock distribution circuit for distributing an input clock according to an embodiment of the present invention includes: a first clock buffer receiving the clock; a first clock mask series-connected to the first clock buffer and controlling clock input to the first clock buffer; a second clock buffer series-connected to the first clock buffer and receiving a clock output from the first clock mask; and a second clock mask series-connected to the first clock buffer and the second clock buffer to control clock input to the second clock buffer.

Abstract: Test circuits, which determine whether memory blocks including at least one redundant block are defective, are included in the memory blocks, respectively. A decoding rule generating circuit so generates a decoding rule that a defective block can not be accessed, and outputs the generated decoding rule as a decoding-rule signal RUL. Under the decoding rule, the redundant address decoder decodes the address signal ADDR, to permit access to the memory blocks except the defective block(s).

Abstract: Test circuits, which determine whether memory blocks including at least one redundant block are defective, are included in the memory blocks, respectively. A decoding rule generating circuit so generates a decoding rule that a defective block can not be accessed, and outputs the generated decoding rule as a decoding-rule signal RUL. Under the decoding rule, the redundant address decoder decodes the address signal ADDR, to permit access to the memory blocks except the defective block(s).

Abstract: A synchronizing circuit is of a master-slave type including a master latch and a slave latch. The master latch latches complementary signals at a rising edge of the clock signal. The slave latch latches the complementary signals output from the master latch at a falling edge of the clock signal. A capacitor is provided between the input node and the output node of each of the master latch and slave latch for assisting signal transition of the output node by the capacitive coupling between the input node and the output node having the same direction in the signal transition.