Patents by Inventor Shinichiro Wada
Shinichiro Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230294643Abstract: A vehicle tank includes a first housing portion configured to house a first liquid for cleaning a cleaning object, and a second housing portion configured to receive a second liquid heated outside by heat exchange with a heating unit of a vehicle and house the second liquid which is received. A first wall defining the first housing portion and a second wall defining the second housing portion have a common wall shared by the first housing portion and the second housing portion.Type: ApplicationFiled: March 14, 2023Publication date: September 21, 2023Inventors: Shinichiro WADA, Kenichiro KANEKO
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Patent number: 8841724Abstract: In an LDMOS transistor, a channel length is reduced to increase a saturation current without causing an off-state breakdown voltage optimized in terms of trade-off between an on-resistance and the off-state breakdown voltage. A short channel region is selectively formed between an element isolation film and a low-concentration body region in which a channel is formed such that the short channel region is located immediately below a gate oxide film. The short channel region has a conduction type opposite to that of the low-concentration body region and has a carrier concentration higher than that of the low-concentration body region. The body region is retreated by the presence of the short channel region toward a high-concentration source region.Type: GrantFiled: December 29, 2010Date of Patent: September 23, 2014Assignee: Hitachi, Ltd.Inventors: Kenji Miyakoshi, Shinichiro Wada, Yohei Yanagida, Takayuki Oshima, Keigo Kitazawa
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Patent number: 8546213Abstract: A high voltage ESD protective diode having high avalanche withstand capability and capable of being formed by using manufacturing steps identical with those for a high voltage transistor to be protected, the device having a structure in which a gate oxide film is formed over a substrate surface at a PN junction formed of an N type low concentration semiconductor substrate constituting a cathode region and a P type low concentration diffusion region constituting an anode region, and a gate electrode which is disposed overriding the gate oxide film and a field oxide film is connected electrically by way of a gate plug with an anode electrode, whereby an electric field at the PN junction is moderated upon avalanche breakdown to obtain a high avalanche withstand capability. Further, the withstand voltage can be adjusted by changing the length of the field oxide film.Type: GrantFiled: December 7, 2010Date of Patent: October 1, 2013Assignee: Hitachi, Ltd.Inventors: Tomoyuki Miyoshi, Shinichiro Wada, Yohei Yanagida
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Patent number: 8525291Abstract: The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply.Type: GrantFiled: June 13, 2012Date of Patent: September 3, 2013Assignee: Hitachi, Ltd.Inventors: Tomoyuki Miyoshi, Shinichiro Wada, Yohei Yanagida
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Patent number: 8368151Abstract: When MOS transistors having a plurality of threshold voltages in which a source and a drain form a symmetrical structure are mounted on the same substrate, electrically-symmetrical characteristics is provided with respect to an exchange of the source and the drain in each MOS transistor. A MOS transistor having a large threshold voltage is provided with a halo diffusion region, and halo implantation is not performed on a MOS transistor having a small threshold voltage.Type: GrantFiled: December 22, 2009Date of Patent: February 5, 2013Assignee: Hitachi, Ltd.Inventors: Kenji Miyakoshi, Shinichiro Wada, Junji Noguchi, Koichiro Miyamoto, Masaya Iida, Masafumi Suefuji
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Publication number: 20120256291Abstract: The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply.Type: ApplicationFiled: June 13, 2012Publication date: October 11, 2012Inventors: Tomoyuki MIYOSHI, Shinichiro Wada, Yohei Yanagida
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Patent number: 8217425Abstract: The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply.Type: GrantFiled: July 20, 2009Date of Patent: July 10, 2012Assignee: Hitachi, Ltd.Inventors: Tomoyuki Miyoshi, Shinichiro Wada, Yohei Yanagida
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Publication number: 20110278669Abstract: Disclosed is a high-voltage diode structure which realizes high reverse recovery capability and high maximum allowable forward current. The distance between a longitudinal end of a p well layer in an anode region and an element isolation region formed to surround the diode is 5 ?m or shorter so as to allow a depletion layer to reach the element isolation region when a maximum rated reverse voltage is applied. During reverse recovery, the electric field strength at an end portion of a p well layer is reduced, hole current is reduced, and local temperature rises are reduced.Type: ApplicationFiled: May 11, 2011Publication date: November 17, 2011Inventors: Tomoyuki MIYOSHI, Shinichiro Wada, Takayuki Oshima, Yohei Yanagida, Takahiro Fujita
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Patent number: 8044488Abstract: The invention is based upon a semiconductor device where a high voltage bipolar transistor is manufactured on the same wafer with a high-speed bipolar transistor, and has a characteristic that the high-speed bipolar transistor and the high voltage bipolar transistor are formed on each epitaxial collector layer having the same thickness and are provided with a buried collector region formed in the same process and having the same impurity profile, the buried collector region exists immediately under a base of the high-speed bipolar transistor, no buried collector region and no SIC region exist immediately under a base of the high voltage bipolar transistor and distance between a base region and a collector plug region of the high voltage bipolar transistor is equal to or is longer than the similar distance of the high-speed bipolar transistor.Type: GrantFiled: June 23, 2008Date of Patent: October 25, 2011Assignees: Hitachi, Ltd., Hitachi Ulsi Systems Co., Ltd.Inventors: Mitsuru Arai, Shinichiro Wada, Hideyuki Hosoe
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Patent number: 8018006Abstract: A semiconductor device includes a lower substrate, a thin semiconductor layer and an insulating layer formed between the lower substrate and the semiconductor layer. An active transistor area is formed with a base formed along a surface of the semiconductor layer, an emitter region formed in the base, a buried collector in the thin semiconductor layer to contact the insulating layer, a collector contacting the buried collector, and emitter, collector and base contacts. The active transistor area is configured to operate at an emitter current at least in the order of mA (milli-ampere). An isolation trench extends through the semiconductor layer to the insulating layer and surrounds the active transistor area with a distance in the order of ?m (micron) from the active transistor area and with a space area of more than 50 ?m2 between the active transistor area and the isolation trench.Type: GrantFiled: April 13, 2010Date of Patent: September 13, 2011Assignees: Hitachi ULSI Systems Co., Ltd., Hitachi, Ltd.Inventors: Mitsuru Arai, Shinichiro Wada, Hideaki Nonami
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Publication number: 20110215401Abstract: In an LDMOS transistor, a channel length is reduced to increase a saturation current without causing an off-state breakdown voltage optimized in terms of trade-off between an on-resistance and the off-state breakdown voltage. A short channel region is selectively formed between an element isolation film and a low-concentration body region in which a channel is formed such that the short channel region is located immediately below a gate oxide film. The short channel region has a conduction type opposite to that of the low-concentration body region and has a carrier concentration higher than that of the low-concentration body region. The body region is retreated by the presence of the short channel region toward a high-concentration source region.Type: ApplicationFiled: December 29, 2010Publication date: September 8, 2011Applicant: Hitachi, Ltd.Inventors: Kenji MIYAKOSHI, Shinichiro Wada, Yohei Yanagida, Takayuki Oshima, Keigo Kitazawa
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Publication number: 20110140199Abstract: A high voltage ESD protective diode having high avalanche withstand capability and capable of being formed by using manufacturing steps identical with those for a high voltage transistor to be protected, the device having a structure in which a gate oxide film is formed over a substrate surface at a PN junction formed of an N type low concentration semiconductor substrate constituting a cathode region and a P type low concentration diffusion region constituting an anode region, and a gate electrode which is disposed overriding the gate oxide film and a field oxide film is connected electrically by way of a gate plug with an anode electrode, whereby an electric field at the PN junction is moderated upon avalanche breakdown to obtain a high avalanche withstand capability. Further, the withstand voltage can be adjusted by changing the length of the field oxide film.Type: ApplicationFiled: December 7, 2010Publication date: June 16, 2011Inventors: Tomoyuki MIYOSHI, Shinichiro Wada, Yohei Yanagida
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Publication number: 20110024838Abstract: There is provided a high withstand voltage LDMOS which is a MOS transistor formed on a semiconductor substrate and isolated by a trench, and a source region of which is sandwiched by a drain region, in which the metal layer gate wire connected to the gate electrode is led out outside the trench so as to pass over a P-type drift layer.Type: ApplicationFiled: July 12, 2010Publication date: February 3, 2011Inventors: Keigo KITAZAWA, Junji Noguchi, Takayuki Oshima, Shinichiro Wada, Tomoyuki Miyoshi, Atsushi Itoh
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Publication number: 20100314712Abstract: A semiconductor device includes a lower substrate, a thin semiconductor layer and an insulating layer formed between the lower substrate and the semiconductor layer. An active transistor area is formed with a base formed along a surface of the semiconductor layer, an emitter region formed in the base, a buried collector in the thin semiconductor layer to contact the insulating layer, a collector contacting the buried collector, and emitter, collector and base contacts. The active transistor area is configured to operate at an emitter current at least in the order of mA (milli-ampere). An isolation trench extends through the semiconductor layer to the insulating layer and surrounds the active transistor area with a distance in the order of ?m (micron) from the active transistor area and with a space area of more than 50 ?m2 between the active transistor area and the isolation trench.Type: ApplicationFiled: April 13, 2010Publication date: December 16, 2010Inventors: Mitsuru Arai, Shinichiro Wada, Hideaki Nonami
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Publication number: 20100186282Abstract: [PROBLEMS] A fishing rod case that can be used for a fishing rod independent of the length of the rod when it is retracted, that can be carried in a form that is as compact as possible according to the length of the fishing rod, and that can sufficiently protect the fishing rod from external force applied while it is carried. [MEANS FOR SOLVING PROBLEMS] An outer case (3) has an opening (4) at one end in the left-right direction. An inner case (2) has an opening (13) at one end in the left-right direction. The opening (13) side of the inner case (2) is inserted into the outer case (3) with the other end of the inner case (2) projected outward from the opening (4). The extent of insertion in the left-right direction of the inner case (2) into the outer case (3) is adjustable. An engagement section (11) formed on either the inner case (2) or the outer case (3) is engaged with an engagement receiver (7) formed in the other, thereby the casts are positional fixed after the extent of insertion is adjusted.Type: ApplicationFiled: January 20, 2006Publication date: July 29, 2010Applicant: AOMORI HOEI INDUSTRIES, LTD.Inventors: Shinichiro Wada, Hayato Takahashi
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Publication number: 20100164015Abstract: When MOS transistors having a plurality of threshold voltages in which a source and a drain form a symmetrical structure are mounted on the same substrate, electrically-symmetrical characteristics is provided with respect to an exchange of the source and the drain in each MOS transistor. A MOS transistor having a large threshold voltage is provided with a halo diffusion region, and halo implantation is not performed on a MOS transistor having a small threshold voltage.Type: ApplicationFiled: December 22, 2009Publication date: July 1, 2010Applicant: HITACHI, LTD.Inventors: Kenji MIYAKOSHI, Shinichiro WADA, Junji NOGUCHI, Koichiro MIYAMOTO, Masaya IIDA, Masafumi SUEFUJI
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Patent number: 7696582Abstract: A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the semiconductor layer, in which a device isolation trench for each of unit bipolar transistors connected in parallel is removed and the plurality of unit bipolar transistors connected in series are entirely surrounded with one device isolation trench.Type: GrantFiled: February 18, 2009Date of Patent: April 13, 2010Assignees: Hitachi ULSI Systems Co., Ltd., Hitachi, Ltd.Inventors: Mitsuru Arai, Shinichiro Wada, Hideaki Nonami
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Publication number: 20100078676Abstract: The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply.Type: ApplicationFiled: July 20, 2009Publication date: April 1, 2010Inventors: Tomoyuki MIYOSHI, Shinichiro WADA, Yohei YANAGIDA
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Patent number: 7569895Abstract: A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the semiconductor layer, in which a device isolation trench for each of unit bipolar transistors connected in parallel is removed and the plurality of unit bipolar transistors connected in series are entirely surrounded with one device isolation trench.Type: GrantFiled: January 19, 2006Date of Patent: August 4, 2009Assignees: Hitachi ULSI Systems Co., Ltd., Hitachi, Ltd.Inventors: Mitsuri Arai, Shinichiro Wada, Hideaki Nonami
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Publication number: 20090184288Abstract: A flocculant including, as a principal component, unit particles obtained by breaking down aggregates of mineral particles in a mineral raw material principally comprising fine particles of a hydrous aluminum silicate including soils or weathering products of rocks including volcanic eruptivesType: ApplicationFiled: January 21, 2008Publication date: July 23, 2009Inventors: Shinichiro WADA, Tatsuo Morimoto, Ai Kuchibune