Patents by Inventor Shin-Jang Shen
Shin-Jang Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8890233Abstract: A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips.Type: GrantFiled: January 31, 2011Date of Patent: November 18, 2014Assignee: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Hang-Ting Lue, Shin-Jang Shen
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Publication number: 20140141583Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.Type: ApplicationFiled: January 28, 2014Publication date: May 22, 2014Applicant: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Shin-Jang Shen, Hang-Ting Lue
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Patent number: 8659944Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.Type: GrantFiled: January 21, 2011Date of Patent: February 25, 2014Assignee: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Shin-Jang Shen, Hang-Ting Lue
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Patent number: 8638636Abstract: One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.Type: GrantFiled: June 16, 2010Date of Patent: January 28, 2014Assignee: Macronix International Co., Ltd.Inventors: Shin-Jang Shen, Bo-Chang Wu, Chuan Ying Yu, Ken-Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
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Patent number: 8531229Abstract: An integrated circuit has a level shifter, a pull-circuit, and a voltage regulator. The level shifter and the pull-up circuit receive power from the same supply voltage. The voltage regulator changes the voltage level from the supply voltage to another voltage level used by the level shifter.Type: GrantFiled: January 31, 2012Date of Patent: September 10, 2013Assignee: Macronix International Co., Ltd.Inventors: Shin-Jang Shen, Lo Chi
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Publication number: 20130194020Abstract: An integrated circuit has a level shifter, a pull-circuit, and a voltage regulator. The level shifter and the pull-up circuit receive power from the same supply voltage. The voltage regulator changes the voltage level from the supply voltage to another voltage level used by the level shifter.Type: ApplicationFiled: January 31, 2012Publication date: August 1, 2013Applicant: Macronix International Co., Ltd.Inventors: Shin-Jang Shen, Lo Chi
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Patent number: 8497710Abstract: A low-offset current-sense amplifier and an operating method thereof are disclosed. The low-offset current-sense amplifier includes a sense amplifier, a first current supply unit, a second current supply unit, and a processing unit. The first current supply unit is coupled to the sense amplifier, and includes a first transistor group and a first current output terminal. The second current supply unit is coupled to the sense amplifier, and includes a second transistor group and a second current output terminal. The processing unit controls the on/off of some transistors of the first transistor group and the second transistor group according to electric currents output from the first current output terminal and the second current output terminal, respectively.Type: GrantFiled: May 16, 2011Date of Patent: July 30, 2013Assignee: National Tsing Hua UniversityInventors: Meng-Fan Cheng, Yu-Fan Lin, Shin-Jang Shen, Yu-Der Chen
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Patent number: 8390365Abstract: A charge pump system for low-supply voltage includes: a clock generator to generate a plurality of clock signals; a clock pump circuit coupled to said clock generator to generate high voltage; a level shifter coupled to said clock generator and said clock pump circuit to generate a plurality of HV (high voltage) clock signals; a main pump circuit coupled to said clock generator and said level shifter to generate output voltage.Type: GrantFiled: October 18, 2010Date of Patent: March 5, 2013Assignee: National Tsing Hua UniversityInventors: Meng-Fan Chang, Shin-Jang Shen, Yi-Lun Lu
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Patent number: 8320211Abstract: A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier.Type: GrantFiled: May 16, 2011Date of Patent: November 27, 2012Assignee: National Tsing Hua UniversityInventors: Meng-Fan Chang, Yu-Fan Lin, Shin-Jang Shen, Yu-Der Chih
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Publication number: 20120293260Abstract: A low-offset current-sense amplifier and an operating method thereof are disclosed. The low-offset current-sense amplifier includes a sense amplifier, a first current supply unit, a second current supply unit, and a processing unit. The first current supply unit is coupled to the sense amplifier, and includes a first transistor group and a first current output terminal. The second current supply unit is coupled to the sense amplifier, and includes a second transistor group and a second current output terminal. The processing unit controls the on/off of some transistors of the first transistor group and the second transistor group according to electric currents output from the first current output terminal and the second current output terminal, respectively.Type: ApplicationFiled: May 16, 2011Publication date: November 22, 2012Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Meng-Fan Chang, Yu-Fan Lin, Shin-Jang Shen, Yu-Der Chih
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Publication number: 20120294090Abstract: A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier.Type: ApplicationFiled: May 16, 2011Publication date: November 22, 2012Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Meng-Fan Chang, Yu-Fan Lin, Shin-Jang Shen, Yu-Der Chih
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Patent number: 8274322Abstract: The present invention discloses a charge pump system with low noise and high output current and voltage, comprising: a four phase clock generator used to generate a first signals group; a serial of delay circuits coupled to said four phase clock generator, wherein each of said delay circuits is coupled to a previous delay circuit relative to each of said delay circuits for delaying a signals group received from said previous delay circuit; a first charge pump circuit coupled to the four phase clock generator and the delay circuits; and an output terminal coupled to the first charge pump circuit; wherein high level of said first signal overlaps two sections of high level of said third signal to generate a first overlapping time and a second overlapping time, and said first overlapping time is not equal to said second overlapping time.Type: GrantFiled: October 18, 2010Date of Patent: September 25, 2012Assignee: National Tsing Hua UniversityInventors: Meng-Fan Chang, Shin-Jang Shen, Wan-Ying Lu
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Patent number: 8169255Abstract: The present invention discloses an offset cancellation current mirror and method thereof. The offset cancellation current minor comprises a first current mirror, a second current minor, switches and resistors. The first current minor comprises two transistors and a capacitance, the capacitance is used to store an electrical potential difference when the switches are turned on in ways of connecting the first current mirror with the resistor. When the switches is turned off in ways of disconnecting the first current mirror with the resistor and connecting the first current mirror with the second current minor, the electrical potential difference stored in the capacitance is used to correct the difference of the two transistors due to manufacture process.Type: GrantFiled: August 31, 2010Date of Patent: May 1, 2012Assignee: National Tsing Hua UniversityInventors: Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu
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Publication number: 20120092063Abstract: The present invention discloses a charge pump system for low-supply voltage including: a clock generator to generate a plurality of clock signals; a clock pump circuit coupled to said clock generator to generate high voltage; a level shifter coupled to said clock generator and said clock pump circuit to generate a plurality of HV (high voltage)-clock signals; a main pump circuit coupled to said clock generator and said level shifter to generate output voltage.Type: ApplicationFiled: October 18, 2010Publication date: April 19, 2012Applicant: National Tsing Hua UniversityInventors: Meng-Fan Chang, Shin-Jang Shen, Yi-Lun Lu
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Publication number: 20120092054Abstract: The present invention discloses a charge pump system with low noise and high output current and voltage, comprising: a four phase clock generator used to generate a first signals group; a serial of delay circuits coupled to said four phase clock generator, wherein each of said delay circuits is coupled to a previous delay circuit relative to each of said delay circuits for delaying a signals group received from said previous delay circuit; a first charge pump circuit coupled to the four phase clock generator and the delay circuits; and an output terminal coupled to the first charge pump circuit; wherein high level of said first signal overlaps two sections of high level of said third signal to generate a first overlapping time and a second overlapping time, and said first overlapping time is not equal to said second overlapping time.Type: ApplicationFiled: October 18, 2010Publication date: April 19, 2012Applicant: National Tsing Hua UniversityInventors: Meng-Fan CHANG, Shin-Jang SHEN, Wan-Ying LU
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Publication number: 20120051137Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.Type: ApplicationFiled: January 21, 2011Publication date: March 1, 2012Applicant: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Shin-Jang Shen, Hang-Ting Lue
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Publication number: 20120049921Abstract: The present invention discloses an offset cancellation current mirror and method thereof. The offset cancellation current minor comprises a first current mirror, a second current minor, switches and resistors. The first current minor comprises two transistors and a capacitance, the capacitance is used to store an electrical potential difference when the switches are turned on in ways of connecting the first current mirror with the resistor. When the switches is turned off in ways of disconnecting the first current mirror with the resistor and connecting the first current mirror with the second current minor, the electrical potential difference stored in the capacitance is used to correct the difference of the two transistors due to manufacture process.Type: ApplicationFiled: August 31, 2010Publication date: March 1, 2012Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu
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Publication number: 20120007167Abstract: A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips.Type: ApplicationFiled: January 31, 2011Publication date: January 12, 2012Inventors: Chun-Hsiung Hung, Hang-Ting Lue, Shin-Jang Shen
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Patent number: 8072244Abstract: The present invention relates to a current sensing amplifier and a method thereof. The current sensing amplifier comprises a first current path, a second current path, a first capacitor, a second capacitor and a latch circuit. When a first current and a second current flow in the first current path and the second current path respectively, the first and second capacitor may be charged by the first current and the second current. The first capacitor and the second capacitor may couple the charged voltage to the transistors in the first current path and the second current path when the first and second current path are cut off so as to cancel the effect of offset voltage of the transistors generated during the manufacturing process.Type: GrantFiled: August 31, 2010Date of Patent: December 6, 2011Assignee: National Tsing Hua UniversityInventors: Chia-Chi Liu, Shin-Jang Shen, Meng-Fan Chang
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Publication number: 20110069571Abstract: One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.Type: ApplicationFiled: June 16, 2010Publication date: March 24, 2011Applicant: Macronix International Co., Ltd.Inventors: Shin-Jang Shen, Bo-Chang Wu, Chuan Ying Yu, Ken-Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung