Patents by Inventor Shin Kiuchi

Shin Kiuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7948725
    Abstract: A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating circuit attenuates the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: May 24, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Shin Kiuchi, Kazuhiko Yoshida, Takeshi Ichimura, Naoki Yaezawa, Shoichi Furuhata
  • Publication number: 20080285188
    Abstract: A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating circuit attenuates the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.
    Type: Application
    Filed: February 22, 2008
    Publication date: November 20, 2008
    Inventors: Shin Kiuchi, Kazuhiko Yoshida, Takeshi Ichimura, Naoki Yaezawa, Shoichi Furuhata
  • Patent number: 7405913
    Abstract: A semiconductor device in includes a transistor and a surge absorption element such as Zener diode, that are formed on the same substrate and connected in parallel. The surge absorption element has a resistance during breakdown operation that is smaller than the resistance of the surge absorption element during breakdown operation of the transistor. In addition, the secondary breakdown current of the surge absorption element is larger than the secondary breakdown current of the transistor. Upon application of a high ESD voltage and high surge voltage, the energy of the ESD and surge is absorbed by operation of the surge absorption element and is limited to a voltage equal to or less than the breakdown voltage of the transistor, which would otherwise be destroyed.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: July 29, 2008
    Assignee: Fuji Electric Device Technology Co.
    Inventors: Hiroshi Tobisaka, Tatsuhiko Fujihira, Shin Kiuchi, Yoshiaki Minoya, Takeshi Ichimura, Naoki Yaezawa, Ryu Saitou, Shouichi Furuhata, Yuichi Harada
  • Patent number: 7352548
    Abstract: A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating/level-shifting circuit attenuates or level-shifts the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating or level-shifting circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: April 1, 2008
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shin Kiuchi, Kazuhiko Yoshida, Takeshi Ichimura, Naoki Yaezawa, Shoichi Furuhata
  • Publication number: 20070285855
    Abstract: A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating/level-shifting circuit attenuates or level-shifts the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating or level-shifting circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.
    Type: Application
    Filed: March 19, 2007
    Publication date: December 13, 2007
    Applicant: FUJI ELECRIC CO., LTD.
    Inventors: Shin Kiuchi, Kazuhiko Yoshida, Takeshi Ichimura, Naoki Yaezawa, Shoichi Furuhata
  • Publication number: 20040238893
    Abstract: A semiconductor device for use in includes a base and emitter shorted by means of a surface electrode. The surface electrode of a vertical-type bipolar transistor in which a P-type epitaxial growth layer and a P-type semiconductor substrate form the collector is electrically connected to the drain electrode of a lateral MOSFET by means of a metal electrode wiring. Upon application of a high ESD voltage and high surge voltage, the energy of the ESD and surge is absorbed by operation of the vertical-type bipolar transistor and is limited to a voltage equal to or less than the breakdown voltage of the lateral MOSFET that was to be destroyed.
    Type: Application
    Filed: March 15, 2004
    Publication date: December 2, 2004
    Inventors: Hiroshi Tobisaka, Tatsuhiko Fujihira, Shin Kiuchi, Yoshiaki Minoya, Takeshi Ichimura, Naoki Yaezawa, Ryu Saitou, Shouichi Furuhata, Yuichi Harada
  • Publication number: 20030063503
    Abstract: A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating/level-shifting circuit attenuates or level-shifts the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating or level-shifting circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.
    Type: Application
    Filed: September 6, 2002
    Publication date: April 3, 2003
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Shin Kiuchi, Kazuhiko Yoshida, Takeshi Ichimura, Naoki Yaezawa, Shoichi Furuhata
  • Publication number: 20030033260
    Abstract: A network sever for facilitates the repair of a product. The server receives information from the network identifying the product to be repaired and receives information from the network identifying a repair class for the product, the repair class having been selected from among a predetermined set of repair classes and characterizing a level difficulty of repair for the product. The server determines an estimated cost of repair for the product, based upon a metric that considers the repair class for the product, tracks the actual amount of time required to repair the product and selectively modifies the metric based upon the actual amount of time tracked.
    Type: Application
    Filed: September 10, 2001
    Publication date: February 13, 2003
    Inventors: Tatsuo Yashiro, Walter T. Inglesby, Shin Kiuchi
  • Patent number: 5621601
    Abstract: The disclosed invention is designed to prevent the oscillation which often occurs in an over-current protection apparatus for an insulated gate controlled transistor. The apparatus improves the response in current detection, to prevent oscillation, and improves protection speed against over-current.
    Type: Grant
    Filed: September 28, 1994
    Date of Patent: April 15, 1997
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tatsuhiko Fujihira, Shin Kiuchi, Kazuhiko Yoshida, Yukio Yano, Kazunori Oyabe, Shoichi Furuhata, Tetsuhiro Morimoto
  • Patent number: 5501517
    Abstract: A current detecting device of the invention has a temperature compensating function used for a current limiting device. A sensing resistance and a reference voltage source are connected to a comparison device. A compensating device, such as semiconductor element, is inserted in series into the reference voltage source in a voltage source circuit for supplying a reference voltage to compensate a temperature dependency of the sensing resistance. Temperature dependency of the reference voltage is a negative temperature dependency in the forward voltage drop. The manufacturing process of the current detecting device becomes simple.
    Type: Grant
    Filed: December 16, 1993
    Date of Patent: March 26, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Shin Kiuchi