Patents by Inventor Shin Kwon

Shin Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240167196
    Abstract: Provided are an epitaxial growth apparatus and a gas supply control module used therefor, the epitaxial growth apparatus including: a reaction chamber; a susceptor positioned in the reaction chamber and configured to seat a wafer thereon; and a gas supply control module configured to control a flow of a gas flowing into the reaction chamber, wherein the gas supply control module includes an injector including a center port corresponding to a central region of the wafer, a pair of edge ports corresponding to both edge regions of the wafer, and a pair of middle ports respectively disposed between the center port and the pair of edge ports, and a flow distribution unit configured to independently distribute the gas flow input from a source module to the ports.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 23, 2024
    Applicant: PJP TECH INC
    Inventors: Bum Ho CHOI, Kyung Shin Park, Hyun Ho Kwon, Dong Hyoun Kim, Suk Ho Lim, Jong Wook Jeong, Seung Soo Lee
  • Patent number: 11976223
    Abstract: An adhesive composition according to an embodiment includes an acrylic copolymer, and a compound containing a sulfide group and having a refractive index of 1.57 or more. The adhesive sheet prepared from the adhesive composition may have a low glass transition temperature and high refractive index, such that an image display device may not include a separate high refractive index pattern layer.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: May 7, 2024
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Kyoung Moon Jung, Hye Rim Kwon, Geon Shin, In Oh Hwang
  • Publication number: 20240136430
    Abstract: A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns; a second active pattern including a second lower pattern and second sheet patterns, a height of the second lower pattern being smaller than a height of the first lower pattern; a first gate structure on the first lower pattern; a second gate structure on the second lower pattern; a first source/drain pattern on the first lower pattern and connected to the first sheet patterns; and a second source/drain pattern on the second lower pattern and connected to the second sheet patterns, wherein a width of an upper surface of the first lower pattern is different from a width of an upper surface of the second lower pattern, and wherein a number of first sheet patterns is different from a number of second sheet patterns.
    Type: Application
    Filed: May 24, 2023
    Publication date: April 25, 2024
    Inventors: Jongmin SHIN, Wook Hyun KWON, Su-Hyeon KIM, Jun Mo PARK, Kyu Bong CHOI
  • Publication number: 20240137790
    Abstract: The present disclosure discloses systems and methods of calculating a near-maximum likelihood detection (MLD) performance capability signal to interference plus noise ratio (SINR) according to instructions stored in non-transitory computer readable memory that when executed by a processor of a multiple-input, multiple output orthogonal frequency-division multiplexing (MIMO-OFDM) wireless communications receiver device cause the processor to perform operations including the processor acquiring Hi and noise variance ?n2 for each subcarrier of a set of subcarriers between a MIMO-OFDM wireless communications transmitter device and the wireless communications receiver device, computing an average received bit mutual information rate (RBIR) over all subcarriers, converting the average RBIR to an effective SINR; and selecting a modulation coding scheme (MCS).
    Type: Application
    Filed: April 4, 2023
    Publication date: April 25, 2024
    Inventors: KYUNG HOON KWON, SEUNG HYEOK AHN, YOUNG HWAN KANG, SEUNG HO CHOO, JUNGCHUL SHIN, DAEHONG KIM
  • Publication number: 20240127865
    Abstract: Disclosed is a charge pump of a flash memory, which includes a first stage pump that is connected between an output terminal and a first pump node, and a second stage pump that is connected between the first pump node and a second pump node. The first stage pump includes a first switch circuit that is connected between a power terminal and the first pump node and provides a power supply voltage to the first pump node in response to a first stage signal, in a normal operation, and a first pump circuit that generates a first pumping voltage by using a voltage of the first pump node in response to a first clock signal and provides the first pumping voltage to the output terminal. The first switch circuit blocks a current flow from the first pump node to the power terminal in a sudden power-off event.
    Type: Application
    Filed: June 30, 2023
    Publication date: April 18, 2024
    Inventors: Yeji Shin, TAE-HONG KWON, YOONJAE LEE, Seokin Hong
  • Publication number: 20240106073
    Abstract: Provided are a separator coating composition for a secondary battery including inorganic particles and a silane salt compound having a specific structure, a separator using the same, and an electrochemical device including the same. Specifically, a separator coating composition for a secondary battery which implements adhesion between an inorganic material layer and a porous substrate without including an acid/polymer-based organic binder in a coating composition for forming the inorganic material layer on one or both surfaces of the porous substrate and does not need a separate dispersing agent for dispersing the inorganic particles, a separator manufactured using the same, and an electrochemical device including the separator are provided.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 28, 2024
    Inventors: Tae Wook KWON, Sang Ick LEE, Won Sub KWACK, Cheol Woo KIM, Hyo Shin KWAK, Heung Taek BAE
  • Patent number: 11779940
    Abstract: Systems, methods and apparatus related to pre-wetting an edge portion of a bonded wafer prior to wetting a flat, horizontal portion of the bonded wafer. The apparatus includes a frame having nozzles directed such that couplant discharged from these nozzles wet the edge of the wafer. The edge nozzles have couplant flow vectors that interface to dampen the trajectory of fluid to reduce splash and pre-wet the edges of the bonded wafer.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: October 10, 2023
    Assignee: Sonix, Inc.
    Inventors: Young-Shin Kwon, Paul Ivan John Keeton, James C. McKeon
  • Publication number: 20230139618
    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, interconnection lines on the cell region and the peripheral region, the interconnection lines being spaced apart from the substrate in a first direction perpendicular to a top surface of the substrate, a lower insulating layer on the cell region and the peripheral region, the lower insulating layer covering the interconnection lines, and a top surface of the lower insulating layer on the cell region being at a lower height than top surfaces of uppermost interconnection lines of the interconnection lines, and data storage patterns on the lower insulating layer on the cell region, the data storage patterns being horizontally spaced apart from each other, and the data storage patterns being connected directly to the top surfaces of the uppermost interconnection lines on the cell region.
    Type: Application
    Filed: July 12, 2022
    Publication date: May 4, 2023
    Inventors: Byoungjae BAE, Shin KWON, Jeongmin PARK, Manjin EOM, Hyungjong JEONG
  • Publication number: 20230097253
    Abstract: The present inventors have arrived at the present application by confirming that a novel quinazolinone derivative exhibits therapeutic efficacy for metabolic disorders. The quinazolinone derivative according to the present application has a similar structure to that of idelalisib, but exhibits very different properties and a different mechanism of action from idelalisib. In addition, this derivative molecule was shown to have excellent efficacy against metabolic disorders, in particular lipid metabolic disorders, through different mechanism of action. The derivative molecule also showed excellent efficacy against non-alcoholic steatohepatitis (NASH). No non-alcoholic steatohepatitis treatment drugs have been approved at the time of filing.
    Type: Application
    Filed: January 22, 2021
    Publication date: March 30, 2023
    Inventors: Jong Woo KIM, Chi Woo LEE, Hye Shin KWON, Sang Hoon KWON, Ukil JU, Yoonseon YOO, Bo Ra CHOI
  • Publication number: 20220254990
    Abstract: A semiconductor device includes a substrate including a first region and a second region, data storage patterns on the first region and spaced apart from each other in a first direction, an upper insulating layer on the first and second regions and on the data storage patterns , a cell line structure penetrating the upper insulating layer on the first region, extending in the first direction, and electrically connected to the data storage patterns, and an upper connection structure penetrating the upper insulating layer on the second region. The upper connection structure includes an upper conductive line, and upper conductive contacts arranged along a bottom surface of the upper conductive line. The bottom surface of the upper conductive line is located at a height higher than a bottom surface of the cell line structure. A side surface of the cell line structure has a straight line shape continuously-extended.
    Type: Application
    Filed: September 29, 2021
    Publication date: August 11, 2022
    Inventors: Kyounghun Ryu, Shin Kwon, Byoungjae Bae, Hyunchul Shin, Gawon Lee
  • Publication number: 20210356439
    Abstract: A coupler and a chuck are described. The chuck is configured to secure an article while the wafer is undergoing an inspection process. The chuck has a plurality of vacuum areas. Some vacuum areas hold the wafer in place while other vacuum areas suction couplant from the edge surface of the wafer. The coupler is used to inspect a surface and subsurface of the wafer for defects and includes a sensing device, which may be a transducer. One or more couplant inlet couplings are disposed on a second portion of the coupler, the couplant inlet couplings provide a couplant to a portion of the wafer inspected by the sensing device. A plurality of vacuum inlet couplings is disposed on a third portion of the coupler. At least one of the vacuum inlet couplings provide suction through a recessed portion of a lower surface of the coupler to remove couplant that is outside the portion of the wafer that is being inspected by the sensing device.
    Type: Application
    Filed: October 3, 2019
    Publication date: November 18, 2021
    Applicant: Sonix, Inc.
    Inventors: Young-Shin Kwon, James Christopher Patrick McKeon, Paul Ivan John Keeton, Michael Lemley Wright
  • Patent number: 10431320
    Abstract: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-Shin Kwon, Jong-Hyoung Lim, Chang-Soo Lee, Chung-Ki Lee
  • Patent number: 10347819
    Abstract: Methods of manufacturing a semiconductor device include forming a conductive layer on a substrate, forming an air gap or other cavity between the conductive layer and the substrate, and patterning the conductive layer to expose the air gap. The methods may further include forming conductive pillars between the substrate and the conductive layer. The air gap may be positioned between the conductive pillars.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongchul Park, Byoungjae Bae, Inho Kim, Shin Kwon, Eunsun Noh, Insun Park, Sangmin Lee
  • Patent number: 9679943
    Abstract: A semiconductor device may include a first magnetic layer including a plurality of first regions configuring a plurality of memory cells and spaced apart from each other on a substrate, and a second region encompassing the plurality of first regions and electrically isolated from the first regions, a tunnel barrier layer disposed on the first magnetic layer, and a second magnetic layer disposed on the tunnel barrier layer.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: June 13, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Chul Park, Shin Jae Kang, Shin Kwon, Kyung Rae Byun
  • Publication number: 20170110203
    Abstract: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.
    Type: Application
    Filed: December 30, 2016
    Publication date: April 20, 2017
    Inventors: HYUNG-SHIN KWON, JONG-HYOUNG LIM, CHANG-SOO LEE, CHUNG-KI LEE
  • Publication number: 20170047509
    Abstract: Methods of manufacturing a semiconductor device include forming a conductive layer on a substrate, forming an air gap or other cavity between the conductive layer and the substrate, and patterning the conductive layer to expose the air gap. The methods may further include forming conductive pillars between the substrate and the conductive layer. The air gap may be positioned between the conductive pillars.
    Type: Application
    Filed: November 1, 2016
    Publication date: February 16, 2017
    Inventors: Jongchul Park, BYOUNGJAE BAE, INHO KIM, SHIN KWON, EUNSUN NOH, INSUN PARK, SANGMIN LEE
  • Patent number: 9515255
    Abstract: Methods of manufacturing a semiconductor device include forming a conductive layer on a substrate, forming an air gap or other cavity between the conductive layer and the substrate, and patterning the conductive layer to expose the air gap. The methods may further include forming conductive pillars between the substrate and the conductive layer. The air gap may be positioned between the conductive pillars.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: December 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongchul Park, Byoungjae Bae, Inho Kim, Shin Kwon, Eunsun Noh, Insun Park, Sangmin Lee
  • Patent number: 9502643
    Abstract: A method of fabricating a semiconductor device includes forming conductive pillars on a substrate, sequentially forming a sacrificial layer and a molding structure between the conductive pillars, forming a conductive layer on the molding structure, such that the conductive layer is connected to the conductive pillars, removing the sacrificial layer to form an air gap, removing the molding structure to form an expanded air gap, and patterning the conductive layer to open the expanded air gap.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: November 22, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoungjae Bae, Jongchul Park, Shin Kwon, Inho Kim, Changwoo Sun
  • Publication number: 20160104745
    Abstract: A semiconductor device may include a first magnetic layer including a plurality of first regions configuring a plurality of memory cells and spaced apart from each other on a substrate, and a second region encompassing the plurality of first regions and electrically isolated from the first regions, a tunnel barrier layer disposed on the first magnetic layer, and a second magnetic layer disposed on the tunnel barrier layer.
    Type: Application
    Filed: May 13, 2015
    Publication date: April 14, 2016
    Inventors: Jong Chul PARK, Shin Jae KANG, Shin KWON, Kyung Rae BYUN
  • Patent number: RE49957
    Abstract: Provided are a method and apparatus for providing and using content advisory (CA) information on Internet contents. A method of providing CA information by using a CA information server, includes receiving a request for the CA information on a content, from an Internet Protocol television (IPTV); searching for CA information on the content; and transmitting the found CA information to the IPTV. A method of using CA information when an IPTV reproduces a content not having the CA information, according to the present invention, includes transmitting a request for CA information, to a CA information server; receiving the CA information from the CA information server; analyzing the CA information; and applying the CA information.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-shin Park, Kwang-hyuk Kim, Sung-wook Ahn, Sung-wook Byun, Sang-woong Lee, Eun-Hee Rhim, O-hoon Kwon, Sung-jin Park, In-chul Hwang, Mun-jo Kim