Patents by Inventor Shin Lin
Shin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240165233Abstract: The present invention relates to a method for reducing localized fat deposits in a subject in need thereof in need thereof by topically treating the subject with rare-earth element doped calcium carbonate particles in combination with low-intensity ultrasound. The rare-earth element doped calcium carbonate particles have good biocompatibility and can increase reactive oxygen species (ROS) production and produce carbon dioxide (CO2) and calcium ions (Ca2+) in the region of administration under the ultrasonic irradiation. The method of the present invention is effective in inducing adipocyte necrosis, inhibiting adipogenesis, and decreasing body weight and useful for body sculpture.Type: ApplicationFiled: November 17, 2022Publication date: May 23, 2024Applicants: National Health Research Institutes, National United University, National Taiwan UniversityInventors: Feng-Huei LIN, Gin-Shin CHEN, Ping-Yu SHIH, Ching-Yun CHEN, Li-Ze LIN, Che-Yung KUAN, Zhi-Yu CHEN, I-Hsuan YANG
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Patent number: 11986285Abstract: A disease diagnosing method and a disease diagnosing system are provided in the disclosure. The disease diagnosing method includes: obtaining continuous images of a body skin and generating a time domain signal according to an average pixel value of a region of interest in each frame of the continuous images; transforming the time domain signal to a frequency domain signal and combining the time domain signal and the frequency domain signal to a time frequency signal; retrieving multiple first features of a first high dimensional space of the time frequency signal to obtain multiple second features of a second high dimensional space; and use the second features as feature vectors to map to a high dimension feature space, and classifying the second features as one of the multiple categories of a disease corresponding to the region of interest in the body skin according to a hyperplane of the high dimension feature space.Type: GrantFiled: October 25, 2021Date of Patent: May 21, 2024Assignee: National Taiwan UniversityInventors: Hao-Ming Hsiao, Hsien-Li Kao, Mao-Shin Lin, Chung-Yuan Hsu
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Publication number: 20240162083Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.Type: ApplicationFiled: January 24, 2024Publication date: May 16, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin LIANG, Chen-Han WANG, Keng-Chu LIN, Tetsuji UENO, Ting-Ting CHEN
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Publication number: 20240158854Abstract: Example spatial transcriptomics techniques use “continuous” polony arrays on a customized gel surface for spatial barcoding. By screening polyacrylamide (PAA) gel fabrication conditions, polonies formed on a crosslinked PAA gel were shown to exhibit a continuous, homogenous DNA distribution, which is highly suited for tissue barcoding applications. Compared with widely used polonies formed in flow cells that utilize linear PAA gels, continuous polonies showed efficient DNA amplification and restriction digestion to generate capture oligo arrays, which have a significantly better spatial RNA capturing performance. In addition, the crosslinked PAA gel showed sufficient constraints on lateral RNA diffusion and provides better mechanical strength and stability for tissue mapping assays than a semifluidic linear PAA gel used by previous methods.Type: ApplicationFiled: March 11, 2022Publication date: May 16, 2024Applicant: University of WashingtonInventors: Liangcai Gu, Xiaonan Fu, Shin Lin, Li Sun
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Publication number: 20240145381Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.Type: ApplicationFiled: January 9, 2024Publication date: May 2, 2024Inventors: Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu
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Patent number: 11972974Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.Type: GrantFiled: January 13, 2022Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sung-Li Wang, Shuen-Shin Liang, Yu-Yun Peng, Fang-Wei Lee, Chia-Hung Chu, Mrunal Abhijith Khaderbad, Keng-Chu Lin
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Publication number: 20240105848Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures, and the semiconductor nanostructures include a first semiconductor material. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the semiconductor nanostructures. The epitaxial structures include a second semiconductor material that is different than the first semiconductor material. The semiconductor device structure further includes a gate stack wrapped around the semiconductor nanostructures.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuen-Shin LIANG, Pang-Yen TSAI, Keng-Chu LIN, Sung-Li WANG, Pinyen LIN
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Publication number: 20240096998Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.Type: ApplicationFiled: November 21, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin LIANG, Chij-chien CHI, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG, Cheng-Wei CHANG, Chein-Shun LIAO, Keng-chu LIN, KAi-Ting HUANG
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Publication number: 20240084450Abstract: A shower head structure and a plasma processing apparatus are provided. The shower head structure includes a plate body with a first zone and a second zone on a first surface. A plurality of first through holes are in the first zone, each of the first through holes having a diameter uniform with others of the first through holes. A plurality of second through holes are in the second zone. The first zone is in connection with the second zone, and the diameter of each of the first through holes is greater than a diameter of each of the second through holes. A plasma processing apparatus includes the shower head structure is also provided.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: HUAN-CHIEH CHEN, JHIH-REN LIN, TAI-PIN LIU, SHYUE-SHIN TSAI, KEITH KUANG-KUO KOAI
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Publication number: 20240087990Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor package. In one embodiment, the method includes providing a first integrated circuit die having a first circuit design on a substrate, providing a second integrated circuit die having a second circuit design on the substrate, wherein the first and second integrated circuit dies are separated from each other by a scribe line.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Shin-Yi YANG, Ming-Han LEE, Shau-Lin SHUE
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Publication number: 20240088042Abstract: A semiconductor structure includes a dielectric layer over a substrate, a via conductor over the substrate and in the dielectric layer, and a first graphene layer disposed over the via conductor. In some embodiments, a top surface of the via conductor and a top surface of the dielectric layer are level. In some embodiments, the first graphene layer overlaps the via conductor from a top view. In some embodiments, the semiconductor structure further includes a second graphene layer under the via conductor and a third graphene layer between the dielectric layer and the via conductor. In some embodiments, the second graphene layer is between the substrate and the via conductor.Type: ApplicationFiled: January 11, 2023Publication date: March 14, 2024Inventors: SHU-WEI LI, HAN-TANG HUNG, YU-CHEN CHAN, CHIEN-HSIN HO, SHIN-YI YANG, MING-HAN LEE, SHAU-LIN SHUE
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Patent number: 11929326Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.Type: GrantFiled: December 20, 2021Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
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Patent number: 11929327Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.Type: GrantFiled: July 22, 2020Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Inc.Inventors: Hsu-Kai Chang, Keng-Chu Lin, Sung-Li Wang, Shuen-Shin Liang, Chia-Hung Chu
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Patent number: 11920190Abstract: Methods of amplifying and determining a target nucleotide sequence are provided. The method of amplifying the target nucleotide sequence includes the following steps. A first adaptor and a second adaptor are linked to two ends of a double-stranded nucleic acid molecule with a target nucleotide sequence respectively to form a nucleic acid template, in which the first adaptor includes a Y-form adaptor or a hairpin adaptor and the second adaptor is a hairpin adaptor. Then, a PCR amplification cycle is performed on the nucleic acid template to obtain a PCR amplicon of the target nucleotide sequence.Type: GrantFiled: December 28, 2020Date of Patent: March 5, 2024Assignee: Industrial Technology Research InstituteInventors: Pei-Shin Jiang, Jenn-Yeh Fann, Hung-Chi Chien, Yu-Yu Lin, Chih-Lung Lin
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Publication number: 20240026957Abstract: A conjugate cam reducer includes input and output units disposed at two opposite sides of a transmission unit. The transmission unit includes smaller-diameter and larger-diameter cam discs axially connected with each other. The smaller-diameter and larger-diameter cam discs have first and second grooves. The input unit includes an input disc, an eccentric shaft and a plurality of input rollers. The input disc has a smaller inner peripheral wall engaging with the smaller-diameter cam disc, and a plurality of first receiving grooves registered with the first grooves to receive the input rollers. The eccentric shaft is rotated to drive rotation of the transmission unit in an eccentric cycloidal motion. The output unit includes an output disc having a larger inner peripheral wall which engages with the larger-diameter cam disc, and a plurality of second receiving grooves which are registered with the second grooves to receive a plurality of output rollers.Type: ApplicationFiled: December 13, 2022Publication date: January 25, 2024Applicant: National Sun Yat-Sen UniversityInventors: Der-Min TSAY, Kun-Lung HSU, Wei-Ming CHEN, Jyun-Ting CHEN, Yuan-Shin LIN
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Publication number: 20230352278Abstract: A plasma-exclusion-zone ring for a substrate processing system that is configured to process a substrate includes a ring-shaped body, an upper portion of the ring-shaped body, a base and a plasma-exclusion-zone ring notch. The upper portion of the ring-shaped body defines a radially inner surface and a top surface. The base of the ring-shaped body defines a radially outer surface, a first bottom surface extending radially inward from the radially outer surface, and a second bottom surface extending radially inward from the first bottom surface. The plasma-exclusion-zone ring notch is proportional to an alignment notch of the substrate. The first bottom surface is tapered and extends at an acute angle from the second bottom surface to the radially outer surface. The first bottom surface is configured to extend over and oppose a periphery of the substrate.Type: ApplicationFiled: March 26, 2021Publication date: November 2, 2023Inventors: Xuefeng HUA, Jack CHEN, Gnanamani AMBUROSE, Dan ZHANG, Chang-Wei HUANG, Chia-Shin LIN
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Patent number: 11795070Abstract: This invention provides processes for treating a mixture of produced water and blowdown water comprising introducing produced water (PW) into blowdown water (BD) for forming a PW-BD water mixture, softening the PW-BD water mixture, subjecting the PW-BD water mixture to activated carbon filtration and reverse osmosis membrane desalination. The process generates a product water and a brine by-product.Type: GrantFiled: September 17, 2021Date of Patent: October 24, 2023Assignee: West Virginia University Board of Governors on behalf of West Virginia UniversityInventor: Lian-Shin Lin
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Patent number: 11786587Abstract: The present invention relates to a composition of subunit dengue vaccine comprising a fusion protein of conjugating or connecting delta C nonstructural protein 1 (NS1?C or truncated NS1?C) to at least one polypeptides of NS3c (or truncated NS3c) and/or consensus envelope protein domain III (cEDIII), thereby enhancing better protection against DENV challenge and alleviating associated pathological effects.Type: GrantFiled: June 19, 2020Date of Patent: October 17, 2023Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Yee-Shin Lin, Trai-Ming Yeh, Yung-Chun Chuang, Chia-Yi Yu, Hsin-Wei Chen, Shu-Wen Wan, Shu-Ying Wang, Tzong-Shiann Ho, Dar-Bin Shieh
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Publication number: 20230317445Abstract: Semiconductor processing methods and apparatuses are provided. Some methods include providing a first wafer to a processing chamber, the first wafer having a thickness, a beveled edge, a first side, and a plurality of devices formed in a device area on the first side, the device area having an outer perimeter, depositing an annular ring of material on the first wafer, the annular ring of material covering a region of the beveled edge and the outer perimeter of the device area, and having an inner boundary closer to the center point of the first wafer than the outer perimeter, bonding a second substrate to the plurality of devices and to a portion of the annular ring of material, and thinning the thickness of the first wafer.Type: ApplicationFiled: August 13, 2021Publication date: October 5, 2023Inventors: Xuefeng Hua, Jack Chen, Ian Scot Latchford, Chia-Shin Lin, Chanthavisa Keovisai
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Publication number: 20230236299Abstract: There is provided a time of flight sensor including a light source, a first pixel, a second pixel and a processor. The first pixel generates a first output signal without receiving reflected light from an external object illuminated by the light source. The second pixel generates a second output signal by receiving the reflected light from the external object illuminated by the light source. The processor calculates deviation compensation and deviation correction associated with temperature variation according to the first output signal to accordingly calibrate a distance calculated according to the second output signal.Type: ApplicationFiled: March 31, 2023Publication date: July 27, 2023Inventors: TSO-SHENG TSAI, YUEH-LIN CHUNG, SHIN-LIN WANG