Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor package. In one embodiment, the method includes providing a first integrated circuit die having a first circuit design on a substrate, providing a second integrated circuit die having a second circuit design on the substrate, wherein the first and second integrated circuit dies are separated from each other by a scribe line.

Abstract: A semiconductor structure includes a dielectric layer over a substrate, a via conductor over the substrate and in the dielectric layer, and a first graphene layer disposed over the via conductor. In some embodiments, a top surface of the via conductor and a top surface of the dielectric layer are level. In some embodiments, the first graphene layer overlaps the via conductor from a top view. In some embodiments, the semiconductor structure further includes a second graphene layer under the via conductor and a third graphene layer between the dielectric layer and the via conductor. In some embodiments, the second graphene layer is between the substrate and the via conductor.

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

Abstract: An improved structure for a tape rule housing is disclosed. The housing is provided with a separately fabricated grip or a grip in one piece with the housing such that the user is able to grasp the grip conveniently and firmly when handling the tape rule instead of holding entire bulky housing unstably. The engagement of separate grip with the housing can be performed in the way of inlaying or sled and channel meshing. Besides, the grip is enclosed with a slip resistant soft cover so as to assure the gripping comfortability and firmness.

Abstract: Tape rule brake mechanism consists of a brake device and a positioning member. The rim of the reel on which a measuring tape being coiled around is provided with at least one trammeling block accompanied with a confinement slot. When the brake machanism is actuated, a detent formed at the tip of the brake device drops into the confinement slot and halt the reel rotation by mating with the trammeling block of the reel so as to indirectly stop motion of the tape coiled on the reel. The tape is stably fixed at the position without slipping away by secure engagement of the positioning member with the detent of the brake device. The reset action of the brake device is assisted by the restoring force of a compressed spring.