Abstract: An on-demand data management system. The system comprises a file management module and a demand analysis module. The file management module receives files. Each file has attributes. The file management module segments the files according the attributes. The demand analysis module receives a data demand and selects data from the segmented files according to the data demand.

Abstract: A touch display panel includes a first substrate, a second substrate, a display medium layer and a touch electrode layer. The touch electrode layer has sensing regions, and each sensing region includes sub-sensing regions. The touch electrode layer includes driving electrode series and sensing electrode series. Each driving electrode series has driving electrodes, and each driving electrode has sub-driving pattern electrodes. The sensing electrode series intersect the driving electrode series. Each sensing electrode series has a plurality of sensing electrode, and each sensing electrode has sub-sensing pattern electrodes.

Abstract: A method of inserting dummy patterns includes providing a window area comprising a main pattern. The main pattern includes first patterns of a first type of features, and second patterns of a second type of features. The first and the second types are different types. The method further includes globally inserting first dummy patterns throughout the window area, wherein the first dummy patterns are dummy patterns of the first type of features; enlarging the main pattern to generate an enlarged main pattern, wherein the enlarged main pattern occupies an enlarged region of the window area; removing the portion of the first dummy patterns in the enlarged region from the first dummy patterns to generate first inversed dummy patterns; and combining the first patterns in the main pattern with the first inversed dummy patterns to generate first mask patterns for the first type of features.

Abstract: A method of inserting dummy patterns includes providing a window area comprising a main pattern. The main pattern includes first patterns of a first type of features, and second patterns of a second type of features. The first and the second types are different types. The method further includes globally inserting first dummy patterns throughout the window area, wherein the first dummy patterns are dummy patterns of the first type of features; enlarging the main pattern to generate an enlarged main pattern, wherein the enlarged main pattern occupies an enlarged region of the window area; removing the portion of the first dummy patterns in the enlarged region from the first dummy patterns to generate first inversed dummy patterns; and combining the first patterns in the main pattern with the first inversed dummy patterns to generate first mask patterns for the first type of features.

Abstract: A method of inserting dummy patterns includes providing a window area comprising a main pattern. The main pattern includes first patterns of a first type of features, and second patterns of a second type of features. The first and the second types are different types. The method further includes globally inserting first dummy patterns throughout the window area, wherein the first dummy patterns are dummy patterns of the first type of features; enlarging the main pattern to generate an enlarged main pattern, wherein the enlarged main pattern occupies an enlarged region of the window area; removing the portion of the first dummy patterns in the enlarged region from the first dummy patterns to generate first inversed dummy patterns; and combining the first patterns in the main pattern with the first inversed dummy patterns to generate first mask patterns for the first type of features.

Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

Abstract: A magnetically operated fan device includes a fan member rotatably supported on a housing, one or more magnetic members disposed in the housing, a base supported in the housing, a follower rotatably attached to the base and having a frame, an axle rotatably attached to the frame and having one or more eccentric members for increasing moment of inertia of the axle, one or more magnetic members attached to the eccentric member for acting with the magnetic members of the housing, to bias the axle to continuously rotate relative to the frame of the follower. A coupling device may couple the axle to the fan member, to have the fan member to be driven continuously by the magnetic members and the eccentric members.

Abstract: An on-demand data management system. The system comprises a file management module and a demand analysis module. The file management module receives files. Each file has attributes. The file management module segments the files according the attributes. The demand analysis module receives a data demand and selects data from the segmented files according to the data demand.

Abstract: Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to a second state. A first writing current is obtained according to a first ratio and the first reference current. A second writing current is obtained according to a second ratio and the second reference current. The memory cell is programmed by applying the first writing current to the first operative line and applying the second writing current to the second operative line.

Abstract: Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to a second state. A first writing current is obtained according to a first ratio and the first reference current. A second writing current is obtained according to a second ratio and the second reference current. The memory cell is programmed by applying the first writing current to the first operative line and applying the second writing current to the second operative line.

Abstract: A method of fabricating an embedded flash memory device. A substrate having a memory area is provided. A device is formed on the substrate in the memory area. A conductive layer is formed over the substrate to cover the device in the memory area. A conformal insulating layer is formed on the conductive layer and the substrate. The insulating layer is removed at an edge of the memory area. By anisotropic etching, the insulating layer and part of the conductive layer is removed to form a control gate on the sidewall of the device. Thus, polysilicon residue caused by the conventional control gate process does not occur.

Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

Abstract: A memory cell including a substrate having a source region; a floating gate structure disposed over the substrate and associated with the source region; and a source coupling enhancement structure covering an exposed portion of the floating gate structure and extending to the source region. The flash memory cell can be fabricated in a method including the steps of forming the floating gate structure over a substrate; forming the source coupling enhancement structure on an exposed portion of the floating gate structure; and forming the source region in the substrate.

Abstract: A method of fabricating an embedded flash memory device. A substrate having a memory area is provided. A device is formed on the substrate in the memory area. A conductive layer is formed over the substrate to cover the device in the memory area. A conformal insulating layer is formed on the conductive layer and the substrate. The insulating layer is removed at an edge of the memory area. By anisotropic etching, the insulating layer and part of the conductive layer is removed to form a control gate on the sidewall of the device. Thus, polysilicon residue caused by the conventional control gate process does not occur.

Abstract: A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.

Abstract: A memory cell including a substrate having a source region; a floating gate structure disposed over the substrate and associated with the source region; and a source coupling enhancement structure covering an exposed portion of the floating gate structure and extending to the source region. The flash memory cell can be fabricated in a method including the steps of forming the floating gate structure over a substrate; forming the source coupling enhancement structure on an exposed portion of the floating gate structure; and forming the source region in the substrate.

Abstract: A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.

Abstract: A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the substrate. An insulating material is used to fill the trench and is then recessed in the trench below the surface of the substrate by polishing and etching steps. A conformal buffer layer is deposited which covers the polysilicon and sidewalls of the trench above the recessed insulating layer. The buffer layer is etched back to expose the insulating layer and the polysilicon is removed by a plasma etch. A spacer comprised of a portion of the buffer layer protects the substrate during the polysilicon etch to prevent unwanted trenches from being formed adjacent to the STI structure, thereby increasing the etch process window.