Patents by Inventor Shine-Kai Tseng
Shine-Kai Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9823801Abstract: A touch panel including a substrate, a plurality of first and second sensing series, and a plurality of conductive repairing pattern layers is provided. The first sensing series are disposed on the substrate and extended along a first direction. Each of the first sensing series includes a plurality of first sensing pads and first bridge lines, and the first bridge lines serially connect two adjacent first sensing pads. The second sensing series are disposed on the substrate and extended along a second direction. Each of the second sensing series includes a plurality of second sensing pads and second bridge lines, and the second bridge lines serially connect two adjacent second sensing pads. Each conductive repairing pattern layer electrically floating locates around the crossover region of the first and second sensing series. Two adjacent sensing pads are connected by the conductive repairing pattern layer after a repair procedure is finished.Type: GrantFiled: August 30, 2016Date of Patent: November 21, 2017Assignee: Au Optronics CorporationInventors: Lih-Hsiung Chan, Shine-Kai Tseng, Chin-Yueh Liao, Hung-Wen Chou
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Publication number: 20160370900Abstract: A touch panel including a substrate, a plurality of first and second sensing series, and a plurality of conductive repairing pattern layers is provided. The first sensing series are disposed on the substrate and extended along a first direction. Each of the first sensing series includes a plurality of first sensing pads and first bridge lines, and the first bridge lines serially connect two adjacent first sensing pads. The second sensing series are disposed on the substrate and extended along a second direction. Each of the second sensing series includes a plurality of second sensing pads and second bridge lines, and the second bridge lines serially connect two adjacent second sensing pads. Each conductive repairing pattern layer electrically floating locates around the crossover region of the first and second sensing series. Two adjacent sensing pads are connected by the conductive repairing pattern layer after a repair procedure is finished.Type: ApplicationFiled: August 30, 2016Publication date: December 22, 2016Applicant: Au Optronics CorporationInventors: Lih-Hsiung Chan, Shine-Kai Tseng, Chin-Yueh Liao, Hung-Wen Chou
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Patent number: 8704220Abstract: An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes.Type: GrantFiled: April 12, 2012Date of Patent: April 22, 2014Assignee: Au Optronics CorporationInventors: Hao-Lin Chiu, Chi-Jui Lin, Shu-Wei Tsao, Chun-Nan Lin, Po-Liang Yeh, Shine-Kai Tseng
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Publication number: 20140106513Abstract: A method of fabricating a TFT includes providing a substrate where a gate, an insulating layer, and a channel layer are formed. A conductive layer is formed on the substrate to cover the channel layer and the insulating layer. A photoresist layer is formed on the conductive layer. A photo mask is placed above the photoresist layer and has a data line pattern, a source pattern, and a drain pattern. A first width (W1) between the source pattern and the drain pattern and a second width (W2) of the data line pattern satisfy the following: if W1?1(um), then W2+a(um), and 0.3<a<0.7. An exposing process is performed by using the photo mask, and a development process is performed to pattern the photoresist layer. The conductive layer is patterned by using the photoresist layer as an etching mask to form a source, a drain, and a data line.Type: ApplicationFiled: December 19, 2013Publication date: April 17, 2014Applicant: Au Optronics CorporationInventors: Huang-Chun Wu, Shine-Kai Tseng
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Patent number: 8698150Abstract: An active device, a driving circuit structure, and a display panel are provided. The active device includes a gate, a gate insulation layer covering the gate, a semiconductor layer disposed above the gate, an etching stop layer disposed on the gate insulation layer and the semiconductor layer, a source, and a drain. The gate forms a meandering pattern on a substrate. The semiconductor layer has an area substantially defining a device region where the active device is. The etching stop layer has a first contact opening and a second contact opening. The first contact opening and the second contact opening separated from each other and both exposing the semiconductor layer. The source and the drain separated from each other are disposed on the etching stop layer and in contact with the semiconductor layer through the first contact opening and the second contact opening, respectively.Type: GrantFiled: October 4, 2012Date of Patent: April 15, 2014Assignee: Au Optronics CorporationInventors: Chao-Yu Yang, Hao-Lin Chiu, Shu-Wei Tsao, Shih-Che Huang, Po-Liang Yeh, Chun-Nan Lin, Shine-Kai Tseng
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Patent number: 8664661Abstract: A method of fabricating a TFT includes providing a substrate where a gate, an insulating layer, and a channel layer are formed. A conductive layer is formed on the substrate to cover the channel layer and the insulating layer. A photoresist layer is formed on the conductive layer. A photo mask is placed above the photoresist layer and has a data line pattern, a source pattern, and a drain pattern. A first width (W1) between the source pattern and the drain pattern and a second width (W2) of the data line pattern satisfy the following: if W1?1(um), then W2+a(um), and 0.3<a<0.7. An exposing process is performed by using the photo mask, and a development process is performed to pattern the photoresist layer. The conductive layer is patterned by using the photoresist layer as an etching mask to form a source, a drain, and a data line.Type: GrantFiled: June 13, 2013Date of Patent: March 4, 2014Assignee: Au Optronics CorporationInventors: Huang-Chun Wu, Shine-Kai Tseng
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Publication number: 20130328069Abstract: An active device, a driving circuit structure, and a display panel are provided. The active device includes a gate, a gate insulation layer covering the gate, a semiconductor layer disposed above the gate, an etching stop layer disposed on the gate insulation layer and the semiconductor layer, a source, and a drain. The gate forms a meandering pattern on a substrate. The semiconductor layer has an area substantially defining a device region where the active device is. The etching stop layer has a first contact opening and a second contact opening. The first contact opening and the second contact opening separated from each other and both exposing the semiconductor layer. The source and the drain separated from each other are disposed on the etching stop layer and in contact with the semiconductor layer through the first contact opening and the second contact opening, respectively.Type: ApplicationFiled: October 4, 2012Publication date: December 12, 2013Applicant: AU OPTRONICS CORPORATIONInventors: Chao-Yu Yang, Hao-Lin Chiu, Shu-Wei Tsao, Shih-Che Huang, Po-Liang Yeh, Chun-Nan Lin, Shine-Kai Tseng
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Publication number: 20130270567Abstract: A method of fabricating a TFT includes providing a substrate where a gate, an insulating layer, and a channel layer are formed. A conductive layer is formed on the substrate to cover the channel layer and the insulating layer. A photoresist layer is formed on the conductive layer. A photo mask is placed above the photoresist layer and has a data line pattern, a source pattern, and a drain pattern. A first width (W1) between the source pattern and the drain pattern and a second width (W2) of the data line pattern satisfy the following: if W1?1(um), then W2+a(um), and 0.3<a<0.7. An exposing process is performed by using the photo mask, and a development process is performed to pattern the photoresist layer. The conductive layer is patterned by using the photoresist layer as an etching mask to form a source, a drain, and a data line.Type: ApplicationFiled: June 13, 2013Publication date: October 17, 2013Inventors: Huang-Chun Wu, Shine-Kai Tseng
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Publication number: 20130119371Abstract: An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes.Type: ApplicationFiled: April 12, 2012Publication date: May 16, 2013Applicant: AU OPTRONICS CORPORATIONInventors: Hao-Lin Chiu, Chi-Jui Lin, Shu-Wei Tsao, Chun-Nan Lin, Po-Liang Yeh, Shine-Kai Tseng
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Patent number: 8349631Abstract: A method for fabricating a TFT array substrate includes following steps. A gate pattern and a first pad pattern are formed on a substrate. A gate insulation layer and a semiconductor layer covering the two patterns are sequentially formed. A patterned photoresist layer having different resist blocks is formed, and patterns and thicknesses of the resist blocks in different regions are adjusted. The semiconductor layer and the gate insulation layer above the first pad pattern are removed through performing an etching process and reducing a thickness of the patterned photoresist layer. After removing the patterned photoresist layer, a source pattern, a drain pattern, and a second pad pattern electrically connected to the first pad pattern are formed. A patterned passivation layer is formed on the gate insulation layer and has a second opening exposing the source pattern or the drain pattern and a third opening exposing the second pad pattern.Type: GrantFiled: September 6, 2011Date of Patent: January 8, 2013Assignee: Au Optronics CorporationInventors: Shine-Kai Tseng, Han-Tu Lin, Shiun-Chang Jan, Kuo-Lung Fang
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Publication number: 20120208305Abstract: A method for fabricating a pixel unit is provided. A TFT is formed on a substrate. A protection layer and a patterned photoresist layer are sequentially formed on the substrate entirely. A patterned protection layer is formed by using the patterned photoresist layer as a mask and partially removing the protection layer, wherein the patterned protection layer has an undercut located at a sidewall thereof A pixel electrode material layer is formed to cover the substrate, the TFT and the patterned photoresist layer, wherein the electrode material layer is disconnected at the undercut and exposes the undercut. A pixel electrode electrically connected to the TFT is formed by lifting off the patterned photoresist layer and parts of the electrode material layer covering the patterned photoresist layer simultaneously through a stripper, wherein the stripper permeates from the undercut to an interface of the patterned photoresist layer and the patterned protection layer.Type: ApplicationFiled: April 24, 2012Publication date: August 16, 2012Applicant: AU OPTRONICS CORPORATIONInventors: Chin-Yueh Liao, Chih-Chun Yang, Chih-Hung Shih, Shine-Kai Tseng
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Publication number: 20120081300Abstract: A touch panel including a substrate, a plurality of first and second sensing series, and a plurality of conductive repairing pattern layers is provided. The first sensing series are disposed on the substrate and extended along a first direction. Each of the first sensing series includes a plurality of first sensing pads and first bridge lines, and the first bridge lines serially connect two adjacent first sensing pads. The second sensing series are disposed on the substrate and extended along a second direction. Each of the second sensing series includes a plurality of second sensing pads and second bridge lines, and the second bridge lines serially connect two adjacent second sensing pads. Each conductive repairing pattern layer electrically floating locates around the crossover region of the first and second sensing series. Two adjacent sensing pads are connected by the conductive repairing pattern layer after a repair procedure is finished.Type: ApplicationFiled: December 17, 2010Publication date: April 5, 2012Applicant: AU OPTRONICS CORPORATIONInventors: Lih-Hsiung Chan, Shine-Kai Tseng, Chin-Yueh Liao, Hung-Wen Chou
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Publication number: 20120037908Abstract: A method of fabricating a TFT includes providing a substrate where a gate, an insulating layer, and a channel layer are formed. A conductive layer is formed on the substrate to cover the channel layer and the insulating layer. A photoresist layer is formed on the conductive layer. A photo mask is placed above the photoresist layer and has a data line pattern, a source pattern, and a drain pattern. A first width (W1) between the source pattern and the drain pattern and a second width (W2) of the data line pattern satisfy the following: if W1?1(um), then W2+a(um), and 0.3<a<0.7. An exposing process is performed by using the photo mask, and a development process is performed to pattern the photoresist layer. The conductive layer is patterned by using the photoresist layer as an etching mask to form a source, a drain, and a data line.Type: ApplicationFiled: September 14, 2010Publication date: February 16, 2012Applicant: AU OPTRONICS CORPORATIONInventors: Huang-Chun Wu, Shine-Kai Tseng
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Publication number: 20110318856Abstract: A method for fabricating a TFT array substrate includes following steps. A gate pattern and a first pad pattern are formed on a substrate. A gate insulation layer and a semiconductor layer covering the two patterns are sequentially formed. A patterned photoresist layer having different resist blocks is formed, and patterns and thicknesses of the resist blocks in different regions are adjusted. The semiconductor layer and the gate insulation layer above the first pad pattern are removed through performing an etching process and reducing a thickness of the patterned photoresist layer. After removing the patterned photoresist layer, a source pattern, a drain pattern, and a second pad pattern electrically connected to the first pad pattern are formed. A patterned passivation layer is formed on the gate insulation layer and has a second opening exposing the source pattern or the drain pattern and a third opening exposing the second pad pattern.Type: ApplicationFiled: September 6, 2011Publication date: December 29, 2011Applicant: Au Optronics CorporationInventors: Shine-Kai Tseng, Han-Tu Lin, Shiun-Chang Jan, Kuo-Lung Fang
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Patent number: 8058087Abstract: A method for fabricating a TFT array substrate includes following steps. A gate pattern and a first pad pattern are formed on a substrate. A gate insulation layer and a semiconductor layer covering the two patterns are sequentially formed. A patterned photoresist layer having different resist blocks is formed, and patterns and thicknesses of the resist blocks in different regions are adjusted. The semiconductor layer and the gate insulation layer above the first pad pattern are removed through performing an etching process and reducing a thickness of the patterned photoresist layer. After removing the patterned photoresist layer, a source pattern, a drain pattern, and a second pad pattern electrically connected to the first pad pattern are formed. A patterned passivation layer is formed on the gate insulation layer and has a second opening exposing the source pattern or the drain pattern and a third opening exposing the second pad pattern.Type: GrantFiled: January 20, 2009Date of Patent: November 15, 2011Assignee: Au Optronics CorporationInventors: Shine-Kai Tseng, Han-Tu Lin, Shiun-Chang Jan, Kuo-Lung Fang
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Publication number: 20110070671Abstract: A method for fabricating a pixel unit is provided. A TFT is formed on a substrate. A protection layer and a patterned photoresist layer are sequentially formed on the substrate entirely. A patterned protection layer is formed by using the patterned photoresist layer as a mask and partially removing the protection layer, wherein the patterned protection layer has an undercut located at a sidewall thereof. A pixel electrode material layer is formed to cover the substrate, the TFT and the patterned photoresist layer, wherein the electrode material layer is disconnected at the undercut and exposes the undercut. A pixel electrode electrically connected to the TFT is formed by lifting off the patterned photoresist layer and parts of the electrode material layer covering the patterned photoresist layer simultaneously through a stripper, wherein the stripper permeates from the undercut to an interface of the patterned photoresist layer and the patterned protection layer.Type: ApplicationFiled: November 24, 2010Publication date: March 24, 2011Applicant: AU OPTRONICS CORPORATIONInventors: Chin-Yueh Liao, Chih-Chun Yang, Chih-Hung Shih, Shine-Kai Tseng
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Publication number: 20110068345Abstract: A pixel unit is disposed on a substrate, and the pixel unit includes a thin film transistor (TFT), a patterned protection layer, and a pixel electrode. The TFT is disposed on the substrate. The patterned protection layer is disposed on the TFT. The patterned protection layer is porous and has an undercut located at a sidewall thereof. The pixel electrode is electrically connected to the TFT.Type: ApplicationFiled: November 24, 2010Publication date: March 24, 2011Applicant: AU OPTRONICS CORPORATIONInventors: Chin-Yueh Liao, Chih-Chun Yang, Chih-Hung Shih, Shine-Kai Tseng
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Publication number: 20100258810Abstract: A method for fabricating a pixel unit is provided. A TFT is formed on a substrate. A protection layer and a patterned photoresist layer are sequentially formed on the substrate entirely. A patterned protection layer is formed by using the patterned photoresist layer as a mask and partially removing the protection layer, wherein the patterned protection layer has an undercut located at a sidewall thereof. A pixel electrode material layer is formed to cover the substrate, the TFT and the patterned photoresist layer, wherein the electrode material layer is disconnected at the undercut and exposes the undercut. A pixel electrode electrically connected to the TFT is formed by lifting off the patterned photoresist layer and parts of the electrode material layer covering the patterned photoresist layer simultaneously through a stripper, wherein the stripper permeates from the undercut to an interface of the patterned photoresist layer and the patterned protection layer.Type: ApplicationFiled: June 10, 2009Publication date: October 14, 2010Applicant: AU OPTRONICS CORPORATIONInventors: Chin-Yueh Liao, Chih-Chun Yang, Chih-Hung Shih, Shine-Kai Tseng
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Publication number: 20100009481Abstract: A method for fabricating a TFT array substrate includes following steps. A gate pattern and a first pad pattern are formed on a substrate. A gate insulation layer and a semiconductor layer covering the two patterns are sequentially formed. A patterned photoresist layer having different resist blocks is formed, and patterns and thicknesses of the resist blocks in different regions are adjusted. The semiconductor layer and the gate insulation layer above the first pad pattern are removed through performing an etching process and reducing a thickness of the patterned photoresist layer. After removing the patterned photoresist layer, a source pattern, a drain pattern, and a second pad pattern electrically connected to the first pad pattern are formed. A patterned passivation layer is formed on the gate insulation layer and has a second opening exposing the source pattern or the drain pattern and a third opening exposing the second pad pattern.Type: ApplicationFiled: January 20, 2009Publication date: January 14, 2010Applicant: Au Optronics CorporationInventors: Shine-Kai Tseng, Han-Tu Lin, Shiun-Chang Jan, Kuo-Lung Fang