Patents by Inventor Shingo Kagami

Shingo Kagami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11838696
    Abstract: A projection system includes a projector that projects a content image and a pattern image, a camera that photographs a projection surface when the pattern image is projected, a camera deformation value calculation unit that calculates a texture deformation value indicating a change in position, orientation, or shape of the projection surface on the basis of a photographing result, a projector deformation value acquisition unit that acquires a projector deformation value for converting the content image on the basis of the pattern image captured in the photographing result and the texture deformation value, and a transmission image acquisition unit that executes processing of deforming the content image on the basis of the projector deformation value and processing of deforming the pattern image on the basis of the projector deformation value, and the pattern image satisfies a condition that a plurality of types of solid color regions having different brightness values are included.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: December 5, 2023
    Assignee: TOHOKU UNIVERSITY
    Inventor: Shingo Kagami
  • Publication number: 20230175840
    Abstract: A three-dimensional shape measuring method includes: a first step to: project first and second projection images on a target object, wherein the first projection images include row-direction stripe patterns different from each other, and the second projection images include column-direction stripe patterns different from each other, and obtain first and second captured images of the target object, wherein the first captured images are captured while the first projection images are projected, and the second captured images are captured while the second projection images are projected; a second step to identify a corresponding projection pixel of the first and second projection images, wherein the corresponding projection pixel corresponds to each of captured pixels of the first and second captured images; and a third step to identify a 3D shape of the target object based on a result of the second step.
    Type: Application
    Filed: December 5, 2022
    Publication date: June 8, 2023
    Applicants: Tohoku University, Konica Minolta, Inc.
    Inventors: Hidechika Ito, Shingo Kagami, Koichi Hashimoto, Daichi Suzuki, Yoshiyuki Toso, Yoshihiro Inagaki
  • Publication number: 20220201263
    Abstract: A projection system includes a projector that projects a content image and a pattern image, a camera that photographs a projection surface when the pattern image is projected, a camera deformation value calculation unit that calculates a texture deformation value indicating a change in position, orientation, or shape of the projection surface on the basis of a photographing result, a projector deformation value acquisition unit that acquires a projector deformation value for converting the content image on the basis of the pattern image captured in the photographing result and the texture deformation value, and a transmission image acquisition unit that executes processing of deforming the content image on the basis of the projector deformation value and processing of deforming the pattern image on the basis of the projector deformation value, and the pattern image satisfies a condition that a plurality of types of solid color regions having different brightness values are included.
    Type: Application
    Filed: August 28, 2020
    Publication date: June 23, 2022
    Inventor: Shingo Kagami
  • Publication number: 20150258684
    Abstract: A robot includes a hand configured to grip a flexible object and a control section configured to cause the hand to operate. The control section causes the hand to operate using relative velocities of the hand and a predetermined section of the flexible object.
    Type: Application
    Filed: March 10, 2015
    Publication date: September 17, 2015
    Inventors: Tomoki HARADA, Shingo KAGAMI, Kotaro OMI
  • Patent number: 8577500
    Abstract: A robot apparatus includes: an image pickup device; a goal-image storing unit that stores, according to sensitivity represented by an amount of change of a pixel value at the time when a target aligned with a goal position on an image at a pixel level is displaced by a displacement amount at a sub-pixel level, goal image data in a state in which the target is arranged; and a target detecting unit that calculates a coincident evaluation value of the target on the basis of comparison of image data including the target and the goal image data stored by the goal-image storing unit and detects positional deviation of the target with respect to the goal position on the basis of the coincidence evaluation value.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: November 5, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Yukihiro Yamaguchi, Shingo Kagami, Kenji Matsunaga, Koichi Hashimoto
  • Publication number: 20120209429
    Abstract: A robot apparatus includes: an image pickup device; a goal-image storing unit that stores, according to sensitivity represented by an amount of change of a pixel value at the time when a target aligned with a goal position on an image at a pixel level is displaced by a displacement amount at a sub-pixel level, goal image data in a state in which the target is arranged; and a target detecting unit that calculates a coincident evaluation value of the target on the basis of comparison of image data including the target and the goal image data stored by the goal-image storing unit and detects positional deviation of the target with respect to the goal position on the basis of the coincidence evaluation value.
    Type: Application
    Filed: February 8, 2012
    Publication date: August 16, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Yukihiro YAMAGUCHI, Shingo KAGAMI, Kenji MATSUNAGA, Koichi HASHIMOTO
  • Patent number: 8244788
    Abstract: A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Masatoshi Ishikawa, Idaku Ishii, Takashi Komuro, Shingo Kagami
  • Patent number: 7244919
    Abstract: A semiconductor integrated circuit device is provided which has a plurality of photo detector circuits and a plurality of processing elements. Each of the photo detector circuits includes a comparing circuit, which compares an output of a photo detector element with a reference voltage. A/D conversion is performed by counting the elapsed time until the output of the photo detector element drops below the reference voltage, and a level of the reference voltage as a function of time to be applied to the comparing circuit and time intervals of the counting are uniquely determined based on given quantization intervals of an amount of current generated by the photo detector element. In addition, the photo detector elements may be reset locally based on the result of the corresponding processing element.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: July 17, 2007
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Masatoshi Ishikawa, Idaku Ishii, Takashi Komuro, Shingo Kagami
  • Patent number: 7098437
    Abstract: A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: August 29, 2006
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Masatoshi Ishikawa, Idaku Ishii, Takashi Komuro, Shingo Kagami
  • Publication number: 20060081767
    Abstract: A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.
    Type: Application
    Filed: November 30, 2005
    Publication date: April 20, 2006
    Inventors: Masatoshi Ishikawa, Idaku Ishii, Takashi Komuro, Shingo Kagami
  • Publication number: 20060081765
    Abstract: A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.
    Type: Application
    Filed: November 30, 2005
    Publication date: April 20, 2006
    Inventors: Masatoshi Ishikawa, Idaku Ishii, Takashi Komuro, Shingo Kagami
  • Publication number: 20030141434
    Abstract: A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.
    Type: Application
    Filed: July 23, 2002
    Publication date: July 31, 2003
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Masatoshi Ishikawa, Idaku Ishii, Takashi Komuro, Shingo Kagami