Abstract: A radiation-hardened reference circuit includes a precision voltage reference circuit for generating a current-controlling voltage at first and second terminals, a driver circuit for receiving the current-controlling voltage at first and second terminals and for generating an output reference voltage, and a differential sampling circuit having first and second input terminals coupled to the first and second terminals of the voltage reference circuit, and first and second output terminals coupled to the first and second terminals of the driver circuit.

Abstract: A sample and hold amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal.

Abstract: A preamplifier includes a differential pair of transistors receiving a bias current having a differential input and a differential output, a first resistor coupled to a first differential output node, a first transistor having a current path coupled between the first resistor and a power supply, a second resistor coupled to the first differential output node, a second transistor having a current path coupled between the second resistor and the power supply, a third resistor coupled to a second differential output node, a third transistor having a current path coupled between the third resistor and the power supply, a fourth resistor coupled to the second differential output node, and a fourth transistor having a current path coupled between the fourth resistor and the power supply, wherein a source of the second and third transistors are coupled together.

Abstract: A sample and hold amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal.

Abstract: A sample and hold amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal.

Abstract: A sample and hold amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal.

Abstract: A preamplifier includes a differential pair of transistors receiving a bias current having a differential input and a differential output, a first resistor coupled to a first differential output node, a first transistor having a current path coupled between the first resistor and a power supply, a second resistor coupled to the first differential output node, a second transistor having a current path coupled between the second resistor and the power supply, a third resistor coupled to a second differential output node, a third transistor having a current path coupled between the third resistor and the power supply, a fourth resistor coupled to the second differential output node, and a fourth transistor having a current path coupled between the fourth resistor and the power supply, wherein a source of the second and third transistors are coupled together.

Abstract: A preamplifier includes a differential pair of transistors receiving a bias current having a differential input and a differential output, a first resistor coupled to a first differential output node, a first transistor having a current path coupled between the first resistor and a power supply, a second resistor coupled to the first differential output node, a second transistor having a current path coupled between the second resistor and the power supply, a third resistor coupled to a second differential output node, a third transistor having a current path coupled between the third resistor and the power supply, a fourth resistor coupled to the second differential output node, and a fourth transistor having a current path coupled between the fourth resistor and the power supply, wherein a source of the second and third transistors are coupled together.

Abstract: A preamplifier includes a differential pair of transistors receiving a bias current having a differential input and a differential output, a first resistor coupled to a first differential output node, a first transistor having a current path coupled between the first resistor and a power supply, a second resistor coupled to the first differential output node, a second transistor having a current path coupled between the second resistor and the power supply, a third resistor coupled to a second differential output node, a third transistor having a current path coupled between the third resistor and the power supply, a fourth resistor coupled to the second differential output node, and a fourth transistor having a current path coupled between the fourth resistor and the power supply, wherein a source of the second and third transistors are coupled together.

Abstract: A radiation-hardened reference circuit includes a precision voltage reference circuit for generating a current-controlling voltage at first and second terminals, a driver circuit for receiving the current-controlling voltage at first and second terminals and for generating an output reference voltage, and a differential sampling circuit having first and second input terminals coupled to the first and second terminals of the voltage reference circuit, and first and second output terminals coupled to the first and second terminals of the driver circuit.

Abstract: A self-biasing reference current generator that is compact and capable of implementation in a bipolar semiconductor process or a CMOS process and that generates a reference current output as well as the bias currents required by the reference current generator itself

Abstract: A self-biasing reference current generator that is compact and capable of implementation in a bipolar semiconductor process or a CMOS process and that generates a reference current output as well as the bias currents required by the reference current generator itself

Abstract: A multi-stage pipeline analog-to-digital converter employs an internal digital domain error detection and calibration algorithm to eliminate accumulated digital truncation errors to thereby improve its accuracy and linearity.

Abstract: A monolithic chip with an integrated circuit forming an 18-bit D/A converter powered by a single supply of +5 volts. The circuit includes a voltage reference producing two stable voltages of 3.5 V and 2.5 V which are directed to a control amplifier. This amplifier produces control signals for the current-source cells of a current-steering network utilizing a segmentation decoder for the three most significant bits, a collector-connected R/2R ladder for the intermediate bits, and an emitter-connected R/2R ladder for the remaining least significant bits. The control signals include one for setting the level of current through an NPN current-source transistor, a second for setting the level of current through a PMOS transistor for turning on or off a pair of switching transistors, and a third for establishing a bias voltage for the turn-on circuits for the NPN current-source transistor.

Abstract: A monolithic chip with an integrated circuit forming an 18-bit D/A converter powered by a single supply of .+-.5 volts. The circuit includes a voltage reference producing two stable voltages of 3.5V and 2.5V which are directed to a control amplifier. This amplifier produces control signals for the current-source cells of a current-steering network utilizing a segmentation decoder for the three most significant bits, a collector-connected R/2R ladder for the intermediate bits, and an emitter-connected R/2R ladder for the remaining least significant bits. The control signals include one for setting the level of current through an NPN current-source transistor, a second for setting the level of current through a PMOS transistor for turning on or off a pair of switching transistors, and a third for establishing a bias voltage for the turn-on circuits for the NPN current-source transistor.

Abstract: A circuit is provided for converting binary information received at first logic high and logic low voltage levels from circuitry of a first logic family into logic high and logic low voltage levels for use by circuitry of a second logic family, and more particularly to a TTL to CMOS converter. A reference stage is provided having a temperature stable reference potential source. The reference potential controls the output from the reference stage which is applied as one input to an input stage, the other input to this stage being the input binary voltage levels. The reference stage output controls the input stage to generate a control potential, the level of which changes when the input voltage level passes through a value which is substantially equal to the reference potential.