Patents by Inventor Shinichi Hodama
Shinichi Hodama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7663186Abstract: A semiconductor device includes: a substrate, a surface portion thereof serving as a drain layer; a first main electrode connected to the drain layer; an epitaxial layer formed on the drain layer; a base layer formed on the epitaxial layer; a source layer formed in a base layer surface portion; an insulated trench sandwiched by base layers; a JFET layer formed on trench side walls; an LDD layer formed in a base layer surface portion and connected to the JFET layer around a top face of the trench; a control electrode formed on a gate insulating film formed on an LDD layer surface part, on surfaces of source layer end parts facing each other across the trench, and on a base layer region sandwiched by the LDD and source layers; and a second main electrode connected to the source and base layers sandwiching the control electrode.Type: GrantFiled: May 9, 2008Date of Patent: February 16, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Yoshihiro Yamaguchi, Yusuke Kawaguchi, Kazutoshi Nakamura, Norio Yasuhara, Kenichi Matsushita, Shinichi Hodama, Akio Nakagawa
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Publication number: 20080251838Abstract: A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the firstType: ApplicationFiled: May 9, 2008Publication date: October 16, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Yoshihiro Yamaguchi, Yusuke Kawaguchi, Kazutoshi Nakamura, Norio Yasuhara, Kenichi Matsushita, Shinichi Hodama, Akio Nakagawa
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Patent number: 7226841Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.Type: GrantFiled: February 18, 2005Date of Patent: June 5, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Izumisawa, Shigeo Kouzuki, Shinichi Hodama
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Patent number: 7061048Abstract: A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.Type: GrantFiled: March 2, 2004Date of Patent: June 13, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kawaguchi, Norio Yasuhara, Syotaro Ono, Shinichi Hodama, Akio Nakagawa
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Patent number: 7061060Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.Type: GrantFiled: March 17, 2003Date of Patent: June 13, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Norio Yasuhara, Syotaro Ono, Kazutoshi Nakamura, Yusuke Kawaguchi, Shinichi Hodama, Akio Nakagawa
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Patent number: 7026214Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.Type: GrantFiled: October 5, 2004Date of Patent: April 11, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Norio Yasuhara, Syotaro Ono, Kazutoshi Nakamura, Yusuke Kawaguchi, Shinichi Hodama, Akio Nakagawa
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Publication number: 20050170587Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.Type: ApplicationFiled: February 18, 2005Publication date: August 4, 2005Inventors: Masaru Izumisawa, Shigeo Kouzuki, Shinichi Hodama
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Patent number: 6878989Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.Type: GrantFiled: May 22, 2002Date of Patent: April 12, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Izumisawa, Shigeo Kouzuki, Shinichi Hodama
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Publication number: 20050056890Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.Type: ApplicationFiled: October 5, 2004Publication date: March 17, 2005Inventors: Norio Yasuhara, Syotaro Ono, Kazutoshi Nakamura, Yusuke Kawaguchi, Shinichi Hodama, Akio Nakagawa
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Publication number: 20040164350Abstract: A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.Type: ApplicationFiled: March 2, 2004Publication date: August 26, 2004Inventors: Yusuke Kawaguchi, Norio Yasuhara, Syotaro Ono, Shinichi Hodama, Akio Nakagawa
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Patent number: 6720618Abstract: A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.Type: GrantFiled: January 28, 2002Date of Patent: April 13, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kawaguchi, Norio Yasuhara, Syotaro Ono, Shinichi Hodama, Akio Nakagawa
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Publication number: 20030227052Abstract: A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the firstType: ApplicationFiled: March 28, 2003Publication date: December 11, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Yoshihiro Yamaguchi, Yusuke Kawaguchi, Kazutoshi Nakamura, Norio Yasuhara, Kenichi Matsushita, Shinichi Hodama, Akio Nakagawa
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Publication number: 20030173620Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.Type: ApplicationFiled: March 17, 2003Publication date: September 18, 2003Inventors: Norio Yasuhara, Syotaro Ono, Kazutoshi Nakamura, Yusuke Kawaguchi, Shinichi Hodama, Akio Nakagawa
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Publication number: 20030089947Abstract: A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.Type: ApplicationFiled: January 28, 2002Publication date: May 15, 2003Inventors: Yusuke Kawaguchi, Norio Yasuhara, Syotaro Ono, Shinichi Hodama, Akio Nakagawa
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Patent number: 6552389Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.Type: GrantFiled: December 13, 2001Date of Patent: April 22, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Norio Yasuhara, Syotaro Ono, Kazutoshi Nakamura, Yusuke Kawaguchi, Shinichi Hodama, Akio Nakagawa
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Publication number: 20020175368Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.Type: ApplicationFiled: May 22, 2002Publication date: November 28, 2002Inventors: Masaru Izumisawa, Shigeo Kouzuki, Shinichi Hodama
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Publication number: 20020100951Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.Type: ApplicationFiled: December 13, 2001Publication date: August 1, 2002Inventors: Norio Yasuhara, Syotaro Ono, Kazutoshi Nakamura, Yusuke Kawaguchi, Shinichi Hodama, Akio Nakagawa